
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
263
Rev 01.24
Table 9-6. RTICTL Field Descriptions
Field
Description
6:4
RTR[6:4]
Real-Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See
Table 9-7.
3:0
RTR[3:0]
Real-Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity.
Table 9-7 shows all possible divide values selectable by the RTICTL register. The
source clock for the RTI is OSCCLK.
Table 9-7. RTI Frequency Divide Rates
RTR[3:0]
RTR[6:4] =
000
(OFF)
001
(210)
010
(211)
011
(212)
100
(213)
101
(214)
110
(215)
111
(216)
0000 (
÷1)
OFF*
210
211
212
213
214
215
216
0001 (
÷2)
OFF*
2x210
2x211
2x212
2x213
2x214
2x215
2x216
0010 (
÷3)
OFF*
3x210
3x211
3x212
3x213
3x214
3x215
3x216
0011 (
÷4)
OFF*
4x210
4x211
4x212
4x213
4x214
4x215
4x216
0100 (
÷5)
OFF*
5x210
5x211
5x212
5x213
5x214
5x215
5x216
0101 (
÷6)
OFF*
6x210
6x211
6x212
6x213
6x214
6x215
6x216
0110 (
÷7)
OFF*
7x210
7x211
7x212
7x213
7x214
7x215
7x216
0111 (
÷8)
OFF*
8x210
8x211
8x212
8x213
8x214
8x215
8x216
1000 (
÷9)
OFF*
9x210
9x211
9x212
9x213
9x214
9x215
9x216
1001 (
÷10)
OFF*
10x210
10x211
10x212
10x213
10x214
10x215
10x216
1010 (
÷11)
OFF*
11x210
11x211
11x212
11x213
11x214
11x215
11x216
1011 (
÷12)
OFF*
12x210
12x211
12x212
12x213
12x214
12x215
12x216
1100 (
÷ 13)
OFF*
13x210
13x211
13x212
13x213
13x214
13x215
13x216
1101 (
÷14)
OFF*
14x210
14x211
14x212
14x213
14x214
14x215
14x216
1110 (
÷15)
OFF*
15x210
15x211
15x212
15x213
15x214
15x215
15x216
1111 (
÷ 16)
OFF*
16x210
16x211
16x212
16x213
16x214
16x215
16x216
* Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility.