
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
340
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24
10.4.7.1
Description of Interrupt Operation
The MSCAN supports four interrupt vectors (see
Table 10-36), any of which can be individually masked
NOTE
The dedicated interrupt vector addresses are dened in the Resets and
Interrupts chapter.
10.4.7.2
Transmit Interrupt
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXEx ag of the empty message buffer is set.
10.4.7.3
Receive Interrupt
A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO.
This interrupt is generated immediately after receiving the EOF symbol. The RXF ag is set. If there are
multiple messages in the receiver FIFO, the RXF ag is set as soon as the next message is shifted to the
foreground buffer.
10.4.7.4
Wake-Up Interrupt
A wake-up interrupt is generated if activity on the CAN bus occurs during MSCN internal sleep mode.
10.4.7.5
Error Interrupt
An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition
conditions:
CAN Status Change — The actual value of the transmit and receive error counters control the
CAN bus state of the MSCAN. As soon as the error counters skip into a critical range (Tx/Rx-
warning, Tx/Rx-error, bus-off) the MSCAN ags an error condition. The status change, which
caused the error condition, is indicated by the TSTAT and RSTAT ags (see
Section 10.3.2.5,Table 10-36. Interrupt Vectors
Interrupt Source
CCR Mask
Local Enable
Wake-Up Interrupt (WUPIF)
I bit
CANRIER (WUPIE)
Error Interrupts Interrupt (CSCIF, OVRIF)
I bit
CANRIER (CSCIE, OVRIE)
Receive Interrupt (RXF)
I bit
CANRIER (RXFIE)
Transmit Interrupts (TXE[2:0])
I bit
CANTIER (TXEIE[2:0])