參數(shù)資料
型號： MC9S12DP512MFU
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Microcontroller Unit (MCU)
中文描述： 微控制器（MCU）
文件頁數(shù)： 108/124頁
文件大?。?/td> 2125K
代理商： MC9S12DP512MFU
MC9S12DP512 Device Guide V01.23
108
The phase detector relationship is given by:
i
ch
is the current in tracking mode.
The loop bandwidth f
C
should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50.
ζ
= 0.9 ensures a good transient response.
And finally the frequency relationship is defined as
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f
C
=10kHz:
2
π
n f
C
K
Φ
The capacitance C
s
can now be calculated as:
The capacitance C
p
should be chosen in the range of:
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in
Figure A-2
. With each transition of the clock f
cmp
, the
deviation from the reference clock f
ref
is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise,voltage,temperatureandotherfactorscauseslightvariationsinthecontrolloopresultinginaclock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in
Figure A-3
.
K
Φ
i
ch
–
K
V
=
=
316.7Hz/
f
C
2
ζ
f
ref
------------------------------------------
π
ζ
1
ζ
2
+
+
1
10
------
f
C
f
C
< 25kHz
f
ref
4 10
-------------
ζ
0.9
=
(
)
;
<
→
<
n
f
VCO
f
ref
-------------
2
synr
1
+
(
)
=
=
= 50
R
----------------------------
=
= 2*
π
*50*10kHz/(316.7Hz/
)
=9.9k
=~10k
C
s
2
ζ
2
π
f
C
R
---------------------
0.516
f
C
R
--------------
ζ
0.9
=
(
)
;
≈
=
= 5.19nF =~ 4.7nF
C
s
20
C
p
C
s
10
≤
≤
C
p
= 470pF
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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