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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MC9S12E128MPVE
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 382/606闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MCU 16BIT 128K FLASH 112-LQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 60
绯诲垪锛� HCS12
鏍稿績铏曠悊鍣細 HCS12
鑺珨灏哄锛� 16-浣�
閫熷害锛� 25MHz
閫i€氭€э細 EBI/EMI锛孖²C锛孲CI锛孲PI
澶栧湇瑷�(sh猫)鍌欙細 POR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 91
绋嬪簭瀛樺劜鍣ㄥ閲忥細 128KB锛�128K x 8锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 8K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.35 V ~ 2.75 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 16x10b; D/A 2x8b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 112-LQFP
鍖呰锛� 鎵樼洡
閰嶇敤锛� M68EVB912E128-ND - BOARD EVAL FOR MC9S12E128/64
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2)
MC9S12E128 Data Sheet, Rev. 1.07
442
Freescale Semiconductor
14.2.3
VDD, VSS 鈥� Regulator Output1 (Core Logic)
Signals VDD/VSS are the primary outputs of VREG3V3V2 that provide the power supply for the core
logic. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF,
X7R ceramic).
In shutdown mode an external supply at VDD/VSS can replace the voltage regulator.
14.2.4
VDDPLL, VSSPLL 鈥� Regulator Output2 (PLL)
Signals VDDPLL/VSSPLL are the secondary outputs of VREG3V3V2 that provide the power supply for the
PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors
(100 nF...220 nF, X7R ceramic).
In shutdown mode an external supply at VDDPLL/VSSPLL can replace the voltage regulator.
14.2.5
VREGEN 鈥� Optional Regulator Enable
This optional signal is used to shutdown VREG3V3V2. In that case VDD/VSS and VDDPLL/VSSPLL must
be provided externally. shutdown mode is entered with VREGEN being low. If VREGEN is high, the
VREG3V3V2 is either in full-performance mode or in reduced-power mode.
For the connectivity of VREGEN see device overview chapter.
NOTE
Switching from FPM or RPM to shutdown of VREG3V3V2 and vice versa
is not supported while the MCU is powered.
14.3
Memory Map and Register Denition
This subsection provides a detailed description of all registers accessible in VREG3V3V2.
14.3.1
Module Memory Map
Figure 14-2 provides an overview of all used registers.
Table 14-2. VREG3V3V2 Memory Map
Address
Offset
Use
Access
0x0000
VREG3V3V2 Control Register (VREGCTRL)
R/W
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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MC9S12E256CPVE 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:HCS12 16-BIT MICROCONTROLLER IC
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