Introduction
MC9S12NE64 Data Sheet, Rev 1.0
Freescale Semiconductor
23
1.1.4
Device Memory Map
Table 1-1 shows the device register map of the MC9S12NE64 after reset. Figure 1-1 illustrates the full
device memory map with FLASH and RAM.
Table 1-1. Device Register Map Overview
Address
Module1
1 Information about the HCS12 core can be found in the MMC, INT, MEBI, BDM, and DBG
block description chapters in this data sheet, and also in the HCS12 CPU Reference
Manual, S12CPUV2/D.
Size
(in Bytes)
$0000 – $0017
CORE (Ports A, B, E, Modes, Inits — MMC, INT,
MEBI)
24
$0018 – $0019
Reserved
2
$001A – $001B
Device ID register (PARTID)
2
$001C – $001F
CORE (MEMSIZ, IRQ, HPRIO — INT, MMC)
4
$0020 – $002F
CORE (DBG)
16
$0030 – $0033
CORE (PPAGE, Port K — MEBI, MMC)
4
$0034 – $003F
Clock and Reset Generator (PLL, RTI, COP)
12
$0040 – $006F
Standard Timer 16-bit 4 channels (TIM)
48
$0070 – $007F
Reserved
16
$0080 – $009F
Analog-to-Digital Converter 10-bit, 8-channel (ATD)
32
$00A0 – $00C7
Reserved
40
$00C8 – $00CF
Serial Communications Interface 0 (SCI0)
8
$00D0 – $00D7
Serial Communications Interface 1 (SCI1)
8
$00D8 – $00DF
Serial Peripheral Interface (SPI)
8
$00E0 – $00E7
Inter IC Bus (IIC)
8
$00E8 – $00FF
Reserved
24
$0100 – $010F
FLASH Control Register
16
$0110 – $011F
Reserved
16
$0120 – $0123
Ethernet Physical Interface (EPHY)
4
$0124 – $013F
Reserved
28
$0140 – $016F
Ethernet Media Access Controller (EMAC)
48
$0170 – $023F
Reserved
208
$0240 – $026F
Port Integration Module (PIM)
48
$0270 – $03FF
Reserved
400