Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
163
Unimplemente
d
R
W
ATDSTAT1
R
CCF7
CCF6
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
W
Unimplemente
d
R
W
ATDDIEN
R
IEN7
IEN6
IEN5
IEN4
IEN3
IEN2
IEN1
IEN0
W
Unimplemente
d
R
W
PORTAD
R
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
W
Left Justied Result Data
Note: The read portion of the left justied result data registers has been divided to show the bit position when reading 10-bit and
ATDDR0H
10-BIT BIT 9 MSB
BIT 7 MSB
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
8-BIT
W
ATDDR0L
10-BIT
BIT 1
U
BIT 0
U
0
8-BIT
W
ATDDR1H
10-BIT BIT 9 MSB
BIT 7 MSB
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
8-BIT
W
ATDDR1L
10-BIT
BIT 1
U
BIT 0
U
0
8-BIT
W
ATDDR2H
10-BIT BIT 9 MSB
BIT 7 MSB
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
8-BIT
W
ATDDR2L
10-BIT
BIT 1
U
BIT 0
U
0
8-BIT
W
ATDDR3H
10-BIT BIT 9 MSB
BIT 7 MSB
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
8-BIT
W
Register
Name
Bit 7
654321
Bit 0
= Unimplemented or Reserved
Figure 5-2. ATD Register Summary (Sheet 2 of 5)