Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
MC9S12XE-Family Reference Manual Rev. 1.21
Freescale Semiconductor
511
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6–3
S8C, S4C,
S2C, S1C
Conversion Sequence Length — These bits control the number of conversions per sequence.
Table 13-11 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity
to HC12 family.
2
FIFO
Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D conversion results map into the result
registers based on the conversion sequence; the result of the rst conversion appears in the rst result register
(ATDDR0), the second result in the second result register (ATDDR1), and so on.
If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conversion
sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning
conversion sequence, the result register counter will wrap around when it reaches the end of the result register
le. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register
le, the current conversion result will be placed.
Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1. So the rst
result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the rst result register
(ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion
(ETRIG=1).
Which result registers hold valid data can be tracked using the conversion complete ags. Fast ag clear mode
may or may not be useful in a particular application to track valid data.
If this bit is one, automatic compare of result registers is always disabled, that is ADC12B16C will behave as if
ACMPIE and all CPME[n] were zero.
0 Conversion results are placed in the corresponding result register up to the selected sequence length.
1 Conversion results are placed in consecutive result registers (wrap around at end).
1–0
FRZ[1:0]
Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the
ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond
to a breakpoint as shown in
Table 13-12. Leakage onto the storage node and comparator reference capacitors
may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.
Table 13-10. Examples of ideal decimal ATD Results
Input Signal
VRL = 0 Volts
VRH = 5.12 Volts
8-Bit
Codes
(resolution=20mV)
10-Bit
Codes
(resolution=5mV)
12-Bit
Codes
(transfer curve has
1.25mV offset)
(resolution=1.25mV)
5.120 Volts
...
0.022
0.020
0.018
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.003
0.002
0.000
255
...
1
0
1023
...
4
3
2
1
0
4095
...
17
16
14
12
11
9
8
6
4
3
2
1
0
Field
Description
Table 13-9. ATDCTL3 Field Descriptions (continued)