Chapter 20 Serial Communication Interface (S12SCIV5)
MC9S12XE-Family Reference Manual Rev. 1.21
Freescale Semiconductor
751
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Figure 20-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample
after the reset is low but is not preceded by three high samples that would qualify as a falling edge.
Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may
set the framing error ag.
Figure 20-26. Start Bit Search Example 5
In
Figure 20-27, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the
noise ag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are
ignored.
Figure 20-27. Start Bit Search Example 6
20.4.6.4
Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it
sets the framing error ag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE ag
because a break character has no stop bit. The FE ag is set at the same time that the RDRF ag is set.
Reset RT Clock
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
2
RT
3
RT
4
RT
7
RT
6
RT
5
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
Samples
RT Clock
RT Clock Count
Start Bit
RXD
11
1
11
0
1
0
LSB
1
00
0
00
0
No Start Bit Found
Reset RT Clock
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
2
RT
3
RT
4
RT
7
RT
6
RT
5
R
T10
RT
9
RT
8
R
T14
R
T13
R
T12
R
T11
R
T15
R
T16
RT
1
RT
2
RT
3
Samples
RT Clock
RT Clock Count
Start Bit
RXD
11
1
11
0
LSB
1
0
11
0