Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual , Rev. 1.21
Freescale Semiconductor
145
1. Read: Anytime.
Write: Anytime.
Table 2-51. DDRH Register Field Descriptions
Field
Description
7
DDRH
Port H data direction—
This register controls the data direction of pin 7.
The enabled SCI5 forces the I/O state to be an output. Depending on the conguration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is congured as output.
0 Associated pin is congured as input.
6
DDRH
Port H data direction—
This register controls the data direction of pin 6.
The enabled SCI5 forces the I/O state to be an input. Depending on the conguration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is congured as output.
0 Associated pin is congured as input.
5
DDRH
Port H data direction—
This register controls the data direction of pin 5.
The enabled SCI4 forces the I/O state to be an output. Depending on the conguration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is congured as output.
0 Associated pin is congured as input.
4
DDRH
Port H data direction—
This register controls the data direction of pin 4.
The enabled SCI4 forces the I/O state to be an input. Depending on the conguration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is congured as output.
0 Associated pin is congured as input.
3
DDRH
Port H data direction—
This register controls the data direction of pin 3.
The enabled SCI7 forces the I/O state to be an output. Depending on the conguration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is congured as output.
0 Associated pin is congured as input.
2
DDRH
Port H data direction—
This register controls the data direction of pin 2.
The enabled SCI7 forces the I/O state to be an input. Depending on the conguration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is congured as output.
0 Associated pin is congured as input.