Chapter 26 384 Kbyte Flash Module (S12XFTM384K2V1)
MC9S12XE-Family Reference Manual , Rev. 1.13
Freescale Semiconductor
1031
fault information will be recorded until the specific ECC fault flag has been cleared. In the event of
simultaneous ECC faults, the priority for fault recording is:
1. Double bit fault over single bit fault
2. CPU over XGATE
All FECCR bits are readable but not writable.
Offset Module Base + 0x000E
76543210
R
ECCR[15:8]
W
Reset
00000000
= Unimplemented or Reserved
Figure 26-20. Flash ECC Error Results High Register (FECCRHI)
Offset Module Base + 0x000F
76543210
R
ECCR[7:0]
W
Reset
00000000
= Unimplemented or Reserved
Figure 26-21. Flash ECC Error Results Low Register (FECCRLO)
Table 26-26. FECCR Index Settings
ECCRIX[2:0]
FECCR Register Content
Bits [15:8]
Bit[7]
Bits[6:0]
000
Parity bits read from
Flash block
CPU or XGATE
source identity
Global address
[22:16]
001
Global address [15:0]
010
Data 0 [15:0]
011
Data 1 [15:0] (P-Flash only)
100
Data 2 [15:0] (P-Flash only)
101
Data 3 [15:0] (P-Flash only)
110
Not used, returns 0x0000 when read
111
Not used, returns 0x0000 when read