參數(shù)資料
型號: MCC68HC711D3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC
封裝: DIE
文件頁數(shù): 128/157頁
文件大?。?/td> 2252K
代理商: MCC68HC711D3
Input/Output (I/O) Ports
Data Sheet
MC68HC711D3 — Rev. 2
72
Input/Output (I/O) Ports
MOTOROLA
5.5.2 Port D Data Direction Register
DDD7–DDD0 — Data Direction for Port D
When port D is a general-purpose I/O port, the DDRD register controls the
direction of the I/O pins as follows:
0 = Configures the corresponding port D pin for input only
1 = Configures the corresponding port D pin for output
In expanded and test modes, bits 6 and 7 are dedicated AS and R/W.
When port D is functioning with the SPI system enabled, bit 5 is dedicated as
the slave select (SS) input. In SPI slave mode, DDD5 has no meaning or effect.
In SPI master mode, DDD5 affects port D bit 5 as follows:
0 = Port D bit 5 is an error-detect input to the SPI.
1 = Port D bit 5 is configured as a general-purpose output line.
If the SPI is enabled and expects port D bits 2, 3, and 4 (MISO, MOSI, and SCK)
to be inputs, then they are inputs, regardless of the state of DDRD bits 2, 3,
and 4. If the SPI expects port D bits 2, 3, and 4 to be outputs, they are outputs
only if DDRD bits 2, 3, and 4 are set.
Address:
$0009
Bit 7
654321
Bit 0
Read:
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
Write:
Reset:
00000000
Figure 5-8. Data Direction Register for Port D (DDRD)
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