參數(shù)資料
型號: MCF51CN128CLK
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 50.33 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 14 MM, 1.40 MM HEIGHT, 0.65 MM PITCH, LQFP-80
文件頁數(shù): 16/48頁
文件大?。?/td> 3550K
代理商: MCF51CN128CLK
Electrical Characteristics
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
23
3.10
Mini-FlexBus Timing Specifications
A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to interface to slave-only
devices up to a maximum bus frequency of 25.1666 MHz. It can be directly connected to asynchronous or synchronous devices
such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional
circuitry. For asynchronous devices a simple chip-select based interface can be used.
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of
a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus frequency.
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Mini-FlexBus output
clock (MB_CLK). All other timing relationships can be derived from these values.
Figure 13. Mini-FlexBus Read Timing
Table 12. Mini-FlexBus AC Timing Specifications
Num
C
Characteristic
Min
Max
Unit
Notes
Frequency of Operation
25.1666
MHz
MB1
D
Clock Period
39.73
ns
MB2
P
Output Valid
20
ns
1
1 Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE.
MB3
D
Output Hold
1.0
ns
MB4
P
Input Setup
22
ns
2
2 Specification is valid for all MB_D[7:0].
MB5
D
Input Hold
10
ns
FB_A[19:16]
FB_CLK
S0
S1
S2
S3
FB_R/W
FB_ALE
DATA[7:0]
8-bit Non-Mux’d Bus
16-bit Mux’d Bus
ADDR[19:0]
ADDR[31:24]
FB_D[7:0]
FB_CSn, FB_OE
S0
FB_AD[15:0]
FB_AD[19:16]
DATA[15:0]
ADDR[19:16]
ADDR[15:0]
MB1
MB2
MB5
MB3
MB4
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