![](http://datasheet.mmic.net.cn/Freescale-Semiconductor/MCF5206FT33A_datasheet_98896/MCF5206FT33A_11.png)
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
vi
USERS MANUAL
MOTOROLA
System Integration Module
7.1
Introduction .......................................................................................... 7-1
7.1.1
Features ..................................................................................... 7-1
7.2
SIM Operation ...................................................................................... 7-1
7.2.1
Module Base Address Register (MBAR) .................................... 7-1
7.2.2
Bus Time-Out Monitor ................................................................ 7-2
7.2.3
Spurious Interrupt Monitor .......................................................... 7-2
7.2.4
Software Watchdog Timer.......................................................... 7-3
7.2.5
Interrupt Controller ..................................................................... 7-3
7.3
Programming Model ............................................................................. 7-6
7.3.1
SIM Registers Memory Map ....................................................... 7-6
7.3.2
SIM Registers ............................................................................. 7-7
7.3.2.1
Module Base Address Register (MBAR) ........................ 7-7
7.3.2.2
SIM Configuration Register (SIMR) ................................ 7-9
7.3.2.3
Interrupt Control Register (ICR) ...................................... 7-9
7.3.2.4
Interrupt Mask Register (IMR) ...................................... 7-11
7.3.2.5
Interrupt-Pending Register (IPR) .................................. 7-12
7.3.2.6
Reset Status Register (RSR) ........................................ 7-13
7.3.2.7
System Protection Control Register (SYPCR) .............. 7-14
7.3.2.8
Software Watchdog Interrupt Vector Reg. (SWIVR)...... 7-15
7.3.2.9
Software Watchdog Service Register (SWSR) ............. 7-16
7.3.2.10
Pin Assignment Register (PAR) ................................... 7-16
Section 8
Chip-Select Module
8.1
Introduction .......................................................................................... 8-1
8.1.1
Features ..................................................................................... 8-1
8.2
Chip Select Module I/O ........................................................................ 8-1
8.2.1
Control Signals ........................................................................... 8-1
8.2.1.1
Chip Select (CS[7:0]) ...................................................... 8-1
8.2.1.2
Write Enable (WE[3:0]) ................................................... 8-1
8.2.1.3
Address Bus ................................................................... 8-3
8.2.1.4
Data Bus ......................................................................... 8-4
8.2.1.5
Transfer Acknowledge (TA) ............................................ 8-4
8.3
Chip Select Operation .......................................................................... 8-4
8.3.1
Chip Select Bank Definition ........................................................ 8-5
8.3.1.1
Base Address and Address Masking .............................. 8-5
8.3.1.2
Access Permissions ....................................................... 8-6
8.3.1.3
Control Features ............................................................. 8-6
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.