MCF5208 ColdFire Microprocessor Data Sheet, Rev. 3 Electrical Characteristics Fr" />
參數(shù)資料
型號(hào): MCF5207CVM166J
廠商: Freescale Semiconductor
文件頁數(shù): 19/46頁
文件大?。?/td> 0K
描述: IC MCU 32BIT RISC 144-MAPBGA
標(biāo)準(zhǔn)包裝: 160
系列: MCF520x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 166.67MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: DMA,WDT
輸入/輸出數(shù): 30
程序存儲(chǔ)器類型: ROMless
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.4 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LBGA
包裝: 托盤
MCF5208 ColdFire Microprocessor Data Sheet, Rev. 3
Electrical Characteristics
Freescale Semiconductor
26
All other timing relationships can be derived from these values. Timings
listed in Table 11 are shown in Figure 14 and Figure 15.
Figure 13. General Input Timing Requirements
5.7.1
FlexBus
FlexBus is a multi-function external bus interface provided to interface to slave-only devices up to a
maximum bus frequency of 83.33 MHz. It can be directly connected to asynchronous or synchronous
devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave)
devices with little or no additional circuitry. For asynchronous devices, a simple chip-select based interface
can be used. The FlexBus interface has six general purpose chip-selects (FB_CS[5:0]) that can be
configured to be distributed between the FlexBus or SDRAM memory interfaces. Chip-select FB_CS[0]
can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or
longword (32 bits) wide. Control signal timing is compatible with common ROM/flash memories.
Invalid
FB_CLK(75MHz)
TSETUP
THOLD
Input Setup And Hold
1.5V
trise
Vh = VIH
Vl = VIL
1.5V
1.5V Valid
tfall
Vh = VIH
Vl = VIL
Input Rise Time
Input Fall Time
* The timings are also valid for inputs sampled on the negative clock edge.
Inputs
FB_CLK
FB4
FB5
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