參數(shù)資料
型號(hào): MCF52100CVM66J
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 45/56頁(yè)
文件大?。?/td> 0K
描述: IC MCU 64K FLASH 66MHZ 81MAPBGA
標(biāo)準(zhǔn)包裝: 240
系列: MCF521xx
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 66MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 81-LBGA
包裝: 托盤
MCF52110 ColdFire Microcontroller, Rev. 1
Family Configurations
Freescale Semiconductor
5
Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 80 MHz processor core frequency
— Up to 40 MHz andoff-chip bus frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A+. This is ISA_A with extensions to support the user stack pointer register and four
new instructions for improved bit processing (ISA_A+)
— Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 16
16 32 or 3232 32 operations
System debug support
— Real-time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) configurable into a 1- or
2-level trigger
On-chip memories
— 16-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply
support
— Up to 128 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses
Power management
— Fully static operation with processor sleep and whole chip stop modes
— Rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Programmable clock enable/disable for each peripheral when not used (except backup watchdog timer)
— Software controlled disable of external clock output for low-power consumption
Three universal asynchronous/synchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity
— Up to two stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
— Transmit and receive FIFO buffers
Two I2C modules
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I2C bus
— Master and slave modes support multiple masters
— Automatic interrupt generation with programmable level
Queued serial peripheral interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to four chip selects available
— Master mode operation only
— Programmable bit rates up to half the CPU clock frequency
— Up to 16 pre-programmed transfers
Fast analog-to-digital converter (ADC)
— Eight analog input channels
— 12-bit resolution
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