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| 型號： | MCF52235CAL60 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 54/55頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 256K FLASH 60MHZ 112-LQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | MCF5223x |
| 核心處理器： | Coldfire V2 |
| 芯體尺寸： | 32-位 |
| 速度： | 60MHz |
| 連通性： | CAN，以太網(wǎng)，I²C，SPI，UART/USART |
| 外圍設(shè)備： | DMA，LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 73 |
| 程序存儲器容量： | 256KB（256K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 112-LQFP |
| 包裝： | 托盤 |
| 配用： | M52235EVB-ND - BOARD EVAL FOR MCF52235 |
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MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10
MCF52235 Family Configurations
Freescale Semiconductor
8
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low power modes
DMA controller
— Four fully programmable channels
— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (4 x 32-bit)
burst transfers
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
— Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4)
Reset
— Separate reset in and reset out signals
— Seven sources of reset:
– Power-on reset (POR)
– External
–Software
– Watchdog
– Loss of clock
– Loss of lock
– Low-voltage detection (LVD)
— Status flag indication of source of last reset
Chip integration module (CIM)
— System configuration during reset
— Selects one of three clock modes
— Configures output pad drive strength
— Unique part identification number and part revision number
General purpose I/O interface
— Up to 56 bits of general purpose I/O
— Bit manipulation supported via set/clear functions
— Programmable drive strengths
— Unused peripheral pins may be used as extra GPIO
JTAG support for system level board testing
1.2.2
V2 Core Overview
The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer. The two-stage
instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is
a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP).
The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage
(AGEX) performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire instruction set architecture revision A+ with added support for a separate user stack
pointer register and four new instructions to assist in bit processing. Additionally, the MCF52235 core includes the enhanced
multiply-accumulate (EMAC) unit for improved signal processing capabilities. The EMAC implements a three-stage arithmetic
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCF52235CAL60A | 制造商:Freescale Semiconductor 功能描述:KIRIN2E EPP - REV A - Bulk |
| MCF52235CVM60 | 功能描述:32位微控制器 - MCU KIRIN2E 121 MAPBGA EPP RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MCF52235DS | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ColdFire Microcontroller |
| MCF52236 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ColdFire Microcontroller |
| MCF52236AF50 | 功能描述:32位微控制器 - MCU 32B 256K FLASH 32KSRAM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
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