UART 13 UCTS1 SYNCA UR" />
參數(shù)資料
型號: MCF52236AF50
廠商: Freescale Semiconductor
文件頁數(shù): 14/55頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 256K FLASH 80-LQFP
標(biāo)準(zhǔn)包裝: 90
系列: MCF5223x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 50MHz
連通性: 以太網(wǎng),I²C,SPI,UART/USART
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲器容量: 256KB(256K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 80-LQFP
包裝: 托盤
MCF5223
5
ColdFire
Mic
roc
ontr
oller,
Re
v
.
1
0
F
reescale
Sem
ic
o
nductor
21
UART 13
UCTS1
SYNCA
URXD2
PUB[3]
PDSR[15]
J3
24
16
URTS1
SYNCB
UTXD2
PUB[2]
PDSR[14]
H3
23
15
URXD1
FEC_TXD[0]
PUB[1]
PDSR[13]
PWOR[2]
K3
32
23
UTXD1
FEC_COL
PUB[0]
PDSR[12]
PWOR[3]
L3
33
24
UART 2
UCTS2
PUC[3]
PDSR[27]
L10
61
URTS2
PUC[2]
PDSR[26]
K10
60
URXD2
PUC[1]
PDSR[25]
K11
62
UTXD2
PUC[0]
PDSR[24]
L11
63
FlexCAN
SYNCA
CANTX4
FEC_MDIO
PAS[3]
PDSR[39]
28
20
SYNCB
CANRX4
FEC_MDC
PAS[2]
PDSR[39]
27
19
VDD5,11
VDD
N/A
D7, E8
65,102
45,74
VDDX
N/A
D5, D6, E6, G5,
G6, G7, H6
14, 43
10, 31
VSS
N/A
E4, E5, E7,F4,
F5, F6, F7, F8
64,101
44,73
VSSX
N/A
15, 42
11, 30
1 The PDSR and PSSR registers are described in Chapter 14, “General Purpose I/O Module. All programmable signals default to 2mA drive in normal
(single-chip) mode.
2 All signals have a pull-up in GPIO mode.
3 The use of an external PHY limits ADC, interrupt, and QSPI functionality. It also disables the UART0/1 and timer pins.
4 The multiplexed CANTX and CANRX signals do not have dedicated pins, but are available as muxed replacements for other signals.
5 The VDD1, VDD2, VDDPLL, and PHY_VDD pins are for decoupling only and should not have power directly applied to them.
6 For primary and GPIO functions only.
7 Only when JTAG mode is enabled.
8 For secondary and GPIO functions only.
9 RSTI has an internal pull-up resistor; however, the use of an external resistor is strongly recommended.
10 For GPIO function. Primary Function has pull-up control within the GPT module.
11 This list for power and ground does not include those dedicated power/ground pins included elsewhere, e.g. in the Ethernet PHY.
Table 3. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group
Primary
Function
SecondaryF
unction
Tertiary
Function
Quaternary
Function
Drive
Strength/
Control1
Wired OR
Control
Pull-up/
Pull-down2
Pin on 121
MAPBGA
Pin on 112
LQFP
Pin on 80
LQFP
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