參數(shù)資料
型號(hào)： MCF52236CAF50
廠商： Freescale Semiconductor
文件頁數(shù)： 16/55頁
文件大小： 0K
描述： IC MCU 32BIT 256K FLASH 80-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： MCF5223x
核心處理器： Coldfire V2
芯體尺寸： 32-位
速度： 50MHz
連通性： 以太網(wǎng)，I²C，SPI，UART/USART
外圍設(shè)備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 56
程序存儲(chǔ)器容量： 256KB（256K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-LQFP
包裝： 托盤
MCF52235 Family Configurations
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10
Freescale Semiconductor
23
1.7
Queued Serial Peripheral Interface (QSPI)
Table 8 describes QSPI signals.
1.8
Fast Ethernet Controller EPHY Signals
Table 9 describes the Fast Ethernet Controller (FEC) signals.
Table 8. Queued Serial Peripheral Interface (QSPI) Signals
Signal Name
Abbreviation
Function
I/O
QSPI Synchronous
Serial Output
QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be
driven on the rising or falling edge of QSPI_CLK.
O
QSPI Synchronous
Serial Data Input
QSPI_DIN
Provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPI_CLK.
I
QSPI Serial Clock
QSPI_CLK
Provides the serial clock from the QSPI. The polarity and phase of
QSPI_CLK are programmable.
O
Synchronous Peripheral
Chip Selects
QSPI_CS[3:0] QSPI peripheral chip selects that can be programmed to be active
high or low.
O
Table 9. Fast Ethernet Controller (FEC) Signals
Signal Name
Abbreviation
Function
I/O
Twisted Pair Input +
RXP
Differential Ethernet twisted-pair input pin. This pin is high-impedance
out of reset.
I
Twisted Pair Input -
RXN
Differential Ethernet twisted-pair input pin. This pin is high-impedance
out of reset.
I
Twisted Pair Output +
TXN
Differential Ethernet twisted-pair output pin. This pin is
high-impedance out of reset.
O
Twisted Pair Output -
TXP
Differential Ethernet twisted-pair output pin. This pin is
high-impedance out of reset.
O
Bias Control Resistor
RBIAS
Connect a 12.4 k
(1.0%) external resistor, RBIAS, between the
PHY_RBIAS pin and analog ground.
Place this resistor as near to the chip pin as possible. Stray
capacitance must be kept to less than 10 pF
(>50 pF causes instability). No high-speed signals can be permitted in
the region of RBIAS.
I
Activity LED
ACT_LED
Indicates when the EPHY is transmitting or receiving
O
Link LED
LINK_LED
Indicates when the EPHY has a valid link
O
Speed LED
SPD_LED
Indicates the speed of the EPHY connection
O
Duplex LED
DUPLED
Indicates the duplex (full or half) of the EPHY connection
O
Collision LED
COLLED
Indicates if the EPHY detects a collision
O
Transmit LED
TXLED
Indicates if the EPHY is transmitting
O
Receive LED
RXLED
Indicates if the EPHY is receiving
O
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