MCF5227x ColdFire Microprocessor Data Sheet, Rev. 8 F" />
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Electrical Characteristics
MCF5227x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
35
S5
SSI_BCLK to SSI_FS output valid
鈥�
10
ns
S6
SSI_BCLK to SSI_FS output invalid
0
鈥�
ns
S7
SSI_BCLK to SSI_TXD valid
鈥�
10
ns
S8
SSI_BCLK to SSI_TXD invalid / high impedence
0
鈥�
ns
S9
SSI_RXD / SSI_FS input setup before SSI_BCLK
10
鈥�
ns
S10
SSI_RXD / SSI_FS input hold after SSI_BCLK
0
鈥�
ns
1 All timings specified with a capactive load of 25pF.
2 SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (SYSCLK).
3 SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the minimum
divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure that SSI_BCLK does not
exceed 4 x fSYS.
Table 27. SSI Timing鈥擲lave Modes1
1 All timings specified with a capactive load of 25 pF.
Num
Characteristic
Symbol
Min
Max
Unit
Notes
S11
SSI_BCLK cycle time
tBCLK
4
脳 1/f
SYS
鈥攏s
S12
SSI_BCLK pulse width high / low
45%
55%
tBCLK
S13
SSI_FS input setup before SSI_BCLK
10
鈥�
ns
S14
SSI_FS input hold after SSI_BCLK
2
鈥�
ns
S15
SSI_BCLK to SSI_TXD / SSI_FS output valid
鈥�
10
ns
S16
SSI_BCLK to SSI_TXD / SSI_FS output invalid / high
impedence
0鈥�
ns
S17
SSI_RXD setup before SSI_BCLK
10
鈥�
ns
S18
SSI_RXD hold after SSI_BCLK
2
鈥�
ns
Table 26. SSI Timing鈥擬aster Modes1 (continued)
Num
Characteristic
Symbol
Min
Max
Unit
Notes
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鍙冩暩(sh霉)鎻忚堪
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