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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MCF52277CVM160 |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 15/46闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU 32BIT 166.67MHZ 196MAPBGA |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | MCF5227x LCD Processors |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 126 |
| 绯诲垪锛� | MCF5227x |
| 鏍稿績铏曠悊鍣細 | Coldfire V2 |
| 鑺珨灏哄锛� | 32-浣� |
| 閫熷害锛� | 166.67MHz |
| 閫ｉ€氭€э細 | CAN锛孍BI/EMI锛孖²C锛孲PI锛孲SI锛孶ART/USART锛孶SB OTG |
| 澶栧湇瑷�(sh猫)鍌欙細 | DMA锛孡CD锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 55 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | ROMless |
| RAM 瀹归噺锛� | 128K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.4 V ~ 1.6 V |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 196-LBGA |
| 鍖呰锛� | 鎵樼洡 |
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MCF5227x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical Characteristics
Freescale Semiconductor
22
NOTE
The processor drives the data lines during the first clock cycle of the transfer with the full
32-bit address. This may be ignored by standard connected devices using non-multiplexed
address and data buses. However, some applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM controller. At
the end of the read and write bus cycles the address signals are indeterminate.
Figure 9. FlexBus Read Timing
FB4
Data Input Setup
tDVFBCH
3.5
鈥�
ns
FB5
Data Input Hold
tDIFBCH
0鈥�
ns
FB6
Transfer Acknowledge (TA) Input Setup
tCVFBCH
4鈥�
ns
FB7
Transfer Acknowledge (TA) Input Hold
tCIFBCH
0鈥�
ns
1 Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2.2, 鈥淒DR SDRAM AC Timing
Specifications,鈥� for SD_CS[3:0] timing.
2 The FlexBus supports programming an extension of the address hold. Please consult the device reference manual for more
information.
Table 13. FlexBus AC Timing Specifications (continued)
Num
Characteristic
Symbol
Min
Max
Unit
Notes
FB_CLK
FB_R/W
S0
S1
S2
S3
FB_TS
FB_A[23:0]
FB_D[31:X]
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
DATA
ADDR[31:X]
ADDR[23:0]
FB3
FB1
FB2
FB5
FB4
FB7
FB6
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| MCF52277CVM160J | 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU 32-BIT MICRO W/LCD-TOUCH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| MCF5232 | 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:Integrated Microprocessor Hardware Specification |
| MCF5232160QFP | 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:Integrated Microprocessor Hardware Specification |
| MCF5232196MAPBGA | 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:Integrated Microprocessor Hardware Specification |
| MCF5232CAB80 | 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU MCF5232 V2CORE 64KSRAM RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324 |
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