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參數(shù)資料
| 型號(hào)： | MCF5232CVM100 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, PBGA196 |
| 封裝： | ROHS COMPLIANT, MAPBGA-196 |
| 文件頁數(shù)： | 4/48頁 |
| 文件大小： | 666K |
| 代理商： | MCF5232CVM100 |
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MCF523x Integrated Microprocessor Hardware Specification, Rev. 4
Design Recommendations
Freescale Semiconductor
12
5.7
Interface Recommendations
5.7.1
SDRAM Controller
5.7.1.1
SDRAM Controller Signals in Synchronous Mode
Table 3 shows the behavior of SDRAM signals in synchronous mode.
5.7.1.2
Address Multiplexing
See the SDRAM controller module chapter in the MCF5235 Reference Manual for details on address
multiplexing.
5.7.2
Ethernet PHY Transceiver Connection
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10
Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3
standard defines and the FEC module supports 18 signals. These are shown in Table 4.
Table 3. Synchronous DRAM Signal Connections
Signal
Description
SD_SRAS
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be
latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM
SD_SRAS. Do not confuse SD_SRAS with the DRAM controller’s SD_CS[1:0], which should not
be interfaced to the SDRAM SD_SRAS signals.
SD_SCAS
Synchronous column address strobe. Indicates a valid column address is present and can be
latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled
SD_SCAS on the SDRAM.
DRAMW
DRAM read/write. Asserted for write operations and negated for read operations.
SD_CS[1:0]
Row address strobe. Select each memory block of SDRAMs connected to the MCF523x. One
SD_CS signal selects one SDRAM block and connects to the corresponding CS signals.
SD_CKE
Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of
SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can
enter a power-down mode where operations are suspended or they can enter self-refresh mode.
SD_CKE functionality is controlled by DCR[COC]. For designs using external multiplexing,
setting COC allows SD_CKE to provide command-bit functionality.
BS[3:0]
Column address strobe. For synchronous operation, BS[3:0] function as byte enables to the
SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs.
CLKOUT
Bus clock output. Connects to the CLK input of SDRAMs.
Table 4. MII Mode
Signal Description
MCF523x Pin
Transmit clock
ETXCLK
Transmit enable
ETXEN
Transmit data
ETXD[3:0]
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| MCF5235CVM100 | 32-BIT, 100 MHz, RISC PROCESSOR, PBGA256 |
| MCF5232CVM150 | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA196 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCF5232CVM100 | 制造商:Freescale Semiconductor 功能描述:Microprocessor IC |
| MCF5232CVM100J | 功能描述:32位微控制器 - MCU V2CORE 64KSRAM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MCF5232CVM150 | 功能描述:微處理器 - MPU MCF5232 V2CORE 64KSRAM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5232CVM150J | 功能描述:32位微控制器 - MCU V2CORE 64KSRAM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MCF5233 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Microprocessor Hardware Specification |
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