參數(shù)資料
型號(hào): MCF5253CVM140J
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 11/34頁(yè)
文件大?。?/td> 0K
描述: IC MCU 2.1MIPS 140MHZ 225MAPBGA
標(biāo)準(zhǔn)包裝: 160
系列: MCF525x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 140MHz
連通性: CAN,EBI/EMI,I²C,QSPI,UART/USART,USB OTG
外圍設(shè)備: DMA,WDT
程序存儲(chǔ)器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.08 V ~ 1.32 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 225-LFBGA
包裝: 托盤
Power Consumption
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4
Freescale Semiconductor
19
5
Power Consumption
Table 18 shows maximum power consumption for the MCF5253 device. Typicals will be supplied at a
later time.
6
Package Information and Pinout
This section includes the pin assignment information, contact connection diagram, and the mechanical
package drawing.
Table 17. JTAG Timing Parameters
ID
Characteristic
Min
Max
Units
TCK Frequency of Operation
0
10
MHz
J1
TCK Cycle Time
100
ns
J2A
TCK Clock Pulse High Width
25
ns
J2B
TCK Clock Pulse Low Width
25
ns
J3A
TCK Fall Time (VIH=2.4 V to VIL=0.5 V)
5
ns
J3B
TCK Rise Time (VIL=0.5 v to VIH=2.4 V)
5
ns
J4
TDI, TMS to TCK rising (Input Setup)
8
ns
J5
TCK rising to TDI, TMS Invalid (Hold)
10
ns
J6
Boundary Scan Data Valid to TCK (Setup)
1
ns
J7
TCK to Boundary Scan Data Invalid to rising edge (Hold)
10
ns
J8
TRST Pulse Width (asynchronous to clock edges)
12
ns
J9
TCK falling to TDO Valid (signal from driven or three-state)
15
ns
J10
TCK falling to TDO High Impedance
2
15
ns
J11
TCK falling to Boundary Scan Data Valid (signal from driven or three-state)
15
ns
J12
TCK falling to Boundary Scan. Data High Impedance
1
15
ns
Table 18. Maximum Power Consumption
Supply
Maximum Current
1.2 V Core
150 mA
3.3 V I/O
(with core supplied separately)
150 mA1
1 This does not include the current required for any externally
connected 3.3V device (e.g., flash, SDRAM, and other I/O
devices).
3.3 V I/O
(with core supplied via internal 1.2 V regulator
which is fed from the 3.3 V supply)
400 mA
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