DMA Timers (DTIM0–DTIM3)
MCF5271 Reference Manual, Rev. 2
22-8
Freescale Semiconductor
22.2.10 DMA Timer Capture Registers (DTCRn)
Each DTCRn, shown in Figure 22-6, latches the corresponding DTCNn value during a capture
operation when an edge occurs on DTINn, as programmed in DTMRn. The system clock is
assumed to be the clock source. DTINn cannot simultaneously function as a clocking source and
as an input capture pin. Indeterminate operation will result if DTINn is set as the clock source
when the input capture mode is used.
22.2.11 DMA Timer Counters (DTCNn)
The current value of the 32-bit DTCNs can be read at anytime without affecting counting. Writing
to DTCNn, shown in
Figure 22-7, clears it. The timer counter increments on the clock source
rising edge (system clock ÷ 1, system clock ÷ 16, or DTINn).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RREF
W
Reset
1111111111111111
15
14
13
12
11
10
987
6543210
RREF
W
Reset
1111111111111111
Address
IPSBAR + 0x00_0404 (DTRR0); IPSBAR + 0x00_0444 (DTRR1);
IPSBAR + 0x00_0484 (DTRR2); IPSBAR + 0x00_04C4 (DTRR3)
Figure 22-5. DMA Timer Reference Registers (DTRRn)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
CAP (32-bit capture counter value)
W
Reset
0000000000000000
15
14
13
12
11
10
987
6543210
R
CAP (32-bit capture counter value)
W
Reset
0000000000000000
Address
IPSBAR + 0x00_0408 (DTCR0); IPSBAR + 0x00_0448 (DTCR1);
IPSBAR + 0x00_0488 (DTCR2); IPSBAR + 0x00_04C8 (DTCR3)
Figure 22-6. DMA Timer Capture Registers (DTCRn)