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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MCF5270VM100
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 432/626闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32BIT 100MHZ 196-MAPBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 126
绯诲垪锛� MCF527x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 100MHz
閫i€氭€э細 EBI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 DMA锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 61
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 ROMless
RAM 瀹归噺锛� 64K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.4 V ~ 1.6 V
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 196-LBGA
鍖呰锛� 鎵樼洡
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I2C Interface
MCF5271 Reference Manual, Rev. 2
25-14
Freescale Semiconductor
25.6.2 Generation of START
After completion of the initialization procedure, serial data can be transmitted by selecting the
master transmitter mode. On a multiple-master bus system, I2SR[IBB] must be tested to determine
whether the serial bus is free. If the bus is free (IBB = 0), the START signal and the first byte (the
slave address) can be sent. The data written to the data register comprises the address of the desired
slave and the lsb indicates the transfer direction.
The free time between a STOP and the next START condition is built into the hardware that
generates the START cycle. Depending on the relative frequencies of the system clock and the
I2C_SCL period, it may be necessary to wait until the I2C is busy after writing the calling address
to the I2DR before proceeding with the following instructions.
The following example signals START and transmits the first byte of data (slave address):
CHFLAG MOVE.B I2SR,-(A0)
;Check I2SR[MBB]
BTST.B #5, (A0)+
BNE.S CHFLAG
;If I2SR[MBB] = 1, wait until it is clear
TXSTART MOVE.B I2CR,-(A0)
;Set transmit mode
BSET.B #4,(A0)
MOVE.B (A0)+, I2CR
MOVE.B I2CR, -(A0)
;Set master mode
BSET.B #5, (A0)
;Generate START condition
MOVE.B (A0)+, I2CR
MOVE.B CALLING,-(A0)
;Transmit the calling address, D0=R/W
MOVE.B (A0)+, I2DR
IFREE
MOVE.B I2SR,-(A0)
;Check I2SR[MBB]
;If it is clear, wait until it is set.
BTST.B #5, (A0)+
BEQ.S IFREE;
25.6.3 Post-Transfer Software Response
Sending or receiving a byte sets the I2SR[ICF], which indicates one byte communication is
finished. I2SR[IIF] is also set. An interrupt is generated if the interrupt function is enabled during
initialization by setting I2CR[IIEN]. Software must first clear I2SR[IIF] in the interrupt routine.
I2SR[ICF] is cleared either by reading from I2DR in receive mode or by writing to I2DR in
transmit mode.
Software can service the I2C I/O in the main program by monitoring IIF if the interrupt function
is disabled. Polling should monitor IIF rather than ICF because that operation is different when
arbitration is lost.
When an interrupt occurs at the end of the address cycle, the master is always in transmit mode;
that is, the address is sent. If master receive mode is required I2CR[MTX] should be toggled.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VI-B6L-IX-B1 CONVERTER MOD DC/DC 28V 75W
VI-B6F-IX-B1 CONVERTER MOD DC/DC 72V 75W
VI-B6B-IX-B1 CONVERTER MOD DC/DC 95V 75W
MC9S12DJ256MPVE IC MCU 256K FLASH 25MHZ 112-LQFP
VI-B64-IW-B1 CONVERTER MOD DC/DC 48V 100W
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