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System Integration Module (SIM)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
6-6
Freescale Semiconductor
6.2.4
System Protection Register (SPR)
The system protection register (SPR),
Figure 6-4, provides information about bus cycles that have
generated error conditions. These error conditions can optionally generate an access error exception by
using the enable bits.
Figure 6-4. System Protection Register (SPR)
3
BusLock
Locks the ownership of the bus.
0 Ownership of the bus is determined by arbitration.
1 Current bus master retains ownership of the bus indefinitely.
2–0
HWR
Hardware watchdog reference. Determines how many clocks to wait before timing out a bus cycle when
SPR[HWTEN] is set. The value programmed should be longer than the response time of the slowest
external peripheral in the system.
000 128
001 256
010 512
011 1024
100 2048
101 4096
110 8192
111 16384
15
14
13
12
11
10
9
8
Field
ADC
WPV
SMV
PE
HWT
RPV
EXT
SUV
Reset
0000_0000
R/W
76
543210
Field ADCEN
WPVEN
SMVEN
PEEN
HWTEN
RPVEN
EXTEN
SUVEN
Reset
0000_1011
R/W
Address
MBAR + 0x006
Table 6-4. SPR Field Descriptions
Bits
Fields
Description
15, 7
ADC,
ADCEN
Address decode conflict. This bit is set when an address matches against two chip selects. If ADCEN is
also set, the bus cycle is terminated with an access error exception.
14, 6
WPV,
WPVEN
Write protect violation. This bit is set when a write access is attempted to an area for which the chip select
is set to read only. If WPVEN is also set, the bus cycle is terminated with an access error exception.
13, 5
SMV,
SMVEN
Stopped module violation. This bit is set when an access is attempted to an on-chip peripheral whose
clock has been stopped. If SMVEN is also set, the bus cycle is terminated with an access error exception.
12, 4
PE, PEEN
Peripheral error. This bit is set when an access to an on-chip peripheral is terminated with a transfer error.
If PEEN is also set, the bus cycle is terminated with an access error exception.
Table 6-3. SCR Field Descriptions (continued)
Bits
Field
Description