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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MCF5272VF66R2J
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 443/544闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32BIT 66MHZ 196-MAPBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 750
绯诲垪锛� MCF527x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 66MHz
閫i€氭€э細 EBI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART锛孶SB
澶栧湇瑷�(sh猫)鍌欙細 DMA锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 32
绋嬪簭瀛樺劜鍣ㄥ閲忥細 16KB锛�4K x 32锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 ROM
RAM 瀹归噺锛� 1K x 32
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 3 V ~ 3.6 V
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 196-LBGA
鍖呰锛� 甯跺嵎 (TR)
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Electrical Characteristics
MCF5272 ColdFire Integrated Microprocessor User鈥檚 Manual, Rev. 3
23-14
Freescale Semiconductor
23.5
SDRAM Interface Timing Specifications
Table 23-10 lists SDRAM interface timings.
Figure 23-9 shows SDRAM timings listed in Table 23-10.
NOTE
Above 48 MHz, the memory bus may need to be configured for one wait
state. It is the responsibility of the user to determine the actual frequency at
which to insert a wait state since this depends on the access time of SRAM
or SDRAM used in a particular system implementation.
Wait states are inserted for SRAM accesses by programming bits 6鈥�2 of the
chip select option registers.
A wait state is added for SDRAM read accesses by setting bit 4 of the
SDRAM control register.
Table 23-10. SDRAM Interface Timing Specifications
Name
Characteristic 1
1 All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0.
0鈥�66 MHz
Unit
Min
Max
Control Inputs
SD1
SDCLK to address output A[22:0] valid
鈥�
13.0
nS
SD2
SDCLK to address output A[22:0] invalid (output hold)
1
鈥�
SD3
SDCLK to DQM[3:0] valid
鈥�
9
nS
SD4
SDCLK to DQM[3:0] invalid (output hold)
1.0
鈥�
SD5
SDCLK to data output (D[31:0]) valid (signal from driven or three-state)
鈥�
13.0
nS
SD6
SDCLK to data output (D[31:0]) invalid (output hold)
1
鈥�
SD7
SDCLK to CAS0, RAS0, SDBA[1:0], SDCLKE, SDRAMWE, valid
鈥�
7
nS
SD8
SDCLK to CAS0, RAS0, SDBA[1:0], SDCLKE, SDRAMWE, invalid (output hold)
1
鈥�
SD9
SDCLK to SDCS valid
鈥�
8
nS
SD10
SDCLK to SDCS invalid (output hold)
1.0
鈥�
SD11
SDCLK to A10_PRECHG valid
鈥�
9.5
SD12
SDCLK to A10_PRECHG invalid (output hold)
1.0
鈥�
SD13
SDCLK to data output (D[31:0]) high impedance
鈥�
6
nS
SD14
Data input (D[31:0]) valid to SDCLK (setup) (pipeline mode, SDRAM control register b4
= 1)
5.5
鈥�
nS
SD15
Data input (D[31:0]) valid to SDCLK (setup) (straight-through mode, SDRAM control
register b4 = 0)
13.0
鈥�
nS
SD16
SDCLK to data input (D[31:0]) invalid (hold)
0
鈥�
nS
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