
Debug Support
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
5-11
15
MAP
Force processor references in emulator mode.
0 All emulator-mode references are mapped into supervisor code and data spaces.
1 The processor maps all references while in emulator mode to a special address space, TT = 10,
TM = 101 or 110.
14
TRC
Force emulation mode on trace exception. If TRC = 1, the processor enters emulator mode when a trace
exception occurs. If TRC=0, the processor enters supervisor mode.
13
EMU
Force emulation mode. If EMU = 1, the processor begins executing in emulator mode. See
Section 5.6.1.1,12–11
DDC
Debug data control. Controls operand data capture for DDATA, which displays the number of bytes defined
by the operand reference size before the actual data; byte displays 8 bits, word displays 16 bits, and long
displays 32 bits (one nibble at a time across multiple clock cycles). See
Table 5-2.
00 No operand data is displayed.
01 Capture all write data.
10 Capture all read data.
11 Capture all read and write data.
10
UHE
User halt enable. Selects the CPU privilege level required to execute the HALT instruction.
0 HALT is a supervisor-only instruction.
1 HALT is a supervisor/user instruction.
9–8
BTB
Branch target bytes. Defines the number of bytes of branch target address DDATA displays.
00 0 bytes
01 Lower 2 bytes of the target address
10 Lower 3 bytes of the target address
11 Entire 4-byte target address
7
—
Reserved, should be cleared.
6
NPL
Non- mode. Determines whether the core operates in pipelined or mode or not.
0 Pipelined mode
1 Nonpipelined mode. The processor effectively executes one instruction at a time with no overlap. This
adds at least 5 cycles to the execution time of each instruction. Given an average execution latency of
1.6, throughput in non-pipeline mode would be 6.6, approximately 25% or less of pipelined performance.
Regardless of the NPL state, a triggered PC breakpoint is always reported before the triggering instruction
executes. In normal pipeline operation, the occurrence of an address and/or data breakpoint trigger is
imprecise. In non-pipeline mode, triggers are always reported before the next instruction begins execution
and trigger reporting can be considered precise.
An address or data breakpoint should always occur before the next instruction begins execution. Therefore
the occurrence of the address/data breakpoints should be guaranteed.
5
IPI
Ignore pending interrupts.
1
Core ignores any pending interrupt requests signalled while in single-instruction-step mode.
0
Core services any pending interrupt requests that were signalled while in single-step mode.
4
SSM
Single-step mode. Setting SSM puts the processor in single-step mode.
0 Normal mode.
1 Single-step mode. The processor halts after execution of each instruction. While halted, any BDM
command can be executed. On receipt of the GO command, the processor executes the next instruction
and halts again. This process continues until SSM is cleared.
3–0
—
Reserved, should be cleared.
Table 5-8. CSR Field Descriptions (continued)
Bit
Name
Description