I2C Interface Freescale Semiconductor 24-5 24.2.4 I
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MCF5280CVF66
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 400/766闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MPU 32BIT 66MHZ 256-BGA
妯欐簴鍖呰锛� 90
绯诲垪锛� MCF528x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 66MHz
閫i€氭€э細 CAN锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART
澶栧湇瑷倷锛� DMA锛孡VD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 142
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 ROMless
RAM 瀹归噺锛� 64K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 3.6 V
鏁�(sh霉)鎿�(j霉)杞夋彌鍣細 A/D 8x10b
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 256-LBGA
鍖呰锛� 鎵樼洡
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I2C Interface
Freescale Semiconductor
24-5
24.2.4
I2C Status Register (I2SR)
I2SR contains bits that indicate transaction direction and status.
IPSBAR
Offset:
0x00_0308 (I2CR)
Access: User read/write
76543210
Reset:
00
000000
Figure 24-4. I2C Control Register (I2CR)
Table 24-4. I2CR Field Descriptions
Field
Description
7
IEN
I2C enable. Controls the software reset of the entire I2C module. If the module is enabled in the middle of a byte
transfer, slave mode ignores the current bus transfer and starts operating when the next START condition is detected.
Master mode is not aware that the bus is busy; initiating a start cycle may corrupt the current bus cycle, ultimately
causing the current master or the I2C module to lose arbitration, after which bus operation returns to normal.
0The I2C module is disabled, but registers can be accessed.
1The I2C module is enabled. This bit must be set before any other I2CR bits have any effect.
6
IIEN
I2C interrupt enable.
0I2C module interrupts are disabled, but currently pending interrupt condition is not cleared.
1I2C module interrupts are enabled. An I2C interrupt occurs if I2SR[IIF] is also set.
5
MSTA
Master/slave mode select bit. If the master loses arbitration, MSTA is cleared without generating a STOP signal.
0 Slave mode. Changing MSTA from 1 to 0 generates a STOP and selects slave mode.
1 Master mode. Changing MSTA from 0 to 1 signals a START on the bus and selects master mode.
4
MTX
Transmit/receive mode select bit. Selects the direction of master and slave transfers.
0 Receive
1 Transmit. When the device is addressed as a slave, software must set MTX according to I2SR[SRW]. In master
mode, MTX must be set according to the type of transfer required. Therefore, when the MCU addresses a slave
device, MTX is always 1.
3
TXAK
Transmit acknowledge enable. Specifies the value driven onto I2C_SDA during acknowledge cycles for master and
slave receivers. Writing TXAK applies only when the I2C bus is a receiver.
0 An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.
1 No acknowledge signal response is sent (acknowledge bit = 1).
2
RSTA
Repeat start. Always read as 0. Attempting a repeat start without bus mastership causes loss of arbitration.
0 No repeat start
1 Generates a repeated START condition.
1
Reserved, must be cleared.
IPSBAR
Offset:
0x00_030C (I2SR)
Access: User read/write
76543210
R
ICF
IAAS
IBB
IAL
0
SRW
IIF
RXAK
W
Reset:
10
000001
Figure 24-5. I2C Status Register (I2SR)
MCF5282 and MCF5216 ColdFire Microcontroller User鈥檚 Manual, Rev. 3
鐩搁棞PDF璩囨枡
PDF鎻忚堪
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MCF5280CVF66J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU V2CORE NO FLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰ㄦ牸:SMD/SMT
MCF5280CVF80 鍔熻兘鎻忚堪:IC MPU 32BIT COLDF 256-MAPBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:MCF528x 妯欐簴鍖呰:250 绯诲垪:56F8xxx 鏍稿績铏曠悊鍣�:56800E 鑺珨灏哄:16-浣� 閫熷害:60MHz 閫i€氭€�:CAN锛孲CI锛孲PI 澶栧湇瑷倷:POR锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):21 绋嬪簭瀛樺劜鍣ㄥ閲�:40KB锛�20K x 16锛� 绋嬪簭瀛樺劜鍣ㄩ鍨�:闁冨瓨 EEPROM 澶у皬:- RAM 瀹归噺:6K x 16 闆诲 - 闆绘簮 (Vcc/Vdd):2.25 V ~ 3.6 V 鏁�(sh霉)鎿�(j霉)杞夋彌鍣�:A/D 6x12b 鎸暕鍣ㄥ瀷:鍏ч儴 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:48-LQFP 鍖呰:鎵樼洡 閰嶇敤:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
MCF5280CVM66 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU MCF5216 V2CORE NOFLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰ㄦ牸:SMD/SMT
MCF5280CVM66J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU V2CORE NO FLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰ㄦ牸:SMD/SMT
MCF5280CVM80 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU MCF5216 V2CORE NOFLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰ㄦ牸:SMD/SMT