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鍨嬭櫉锛� MCF5280CVM80
寤犲晢锛� Freescale Semiconductor
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I2C Interface
24-12
Freescale Semiconductor
24.3.8
Handshaking and Clock Stretching
The clock synchronization mechanism can acts as a handshake in data transfers. Slave devices can hold
I2C_SCL low after completing one byte transfer. In such a case, the clock mechanism halts the bus clock
and forces the master clock into wait states until the slave releases I2C_SCL.
Slaves may also slow down the transfer bit rate. After the master has driven I2C_SCL low, the slave can
drive I2C_SCL low for the required period and then release it. If the slave I2C_SCL low period is longer
than the master I2C_SCL low period, the resulting I2C_SCL bus signal low period is stretched.
24.4
Initialization/Application Information
The following examples show programming for initialization, signaling START, post-transfer software
response, signaling STOP, and generating a repeated START.
24.4.1
Initialization Sequence
Before the interface can transfer serial data, registers must be initialized:
1. Set I2FDR[IC] to obtain I2C_SCL frequency from the system bus clock. See Section 24.2.2, 鈥淚2C
2. Update the I2ADR to define its slave address.
3. Set I2CR[IEN] to enable the I2C bus interface system.
4. Modify the I2CR to select or deselect master/slave mode, transmit/receive mode, and
interrupt-enable or not.
NOTE
If I2SR[IBB] is set when the I2C bus module is enabled, execute the
following pseudocode sequence before proceeding with normal
initialization code. This issues a STOP command to the slave device,
placing it in idle state as if it were power-cycled on.
I2CR = 0x0
I2CR = 0xA0
dummy read of I2DR
I2SR = 0x0
I2CR = 0x0
I2CR = 0x80
; re-enable
24.4.2
Generation of START
After completion of the initialization procedure, serial data can be transmitted by selecting the master
transmitter mode. On a multiple-master bus system, I2SR[IBB] must be tested to determine whether the
serial bus is free. If the bus is free (IBB is cleared), the START signal and the first byte (the slave address)
can be sent. The data written to the data register comprises the address of the desired slave and the lsb
indicates the transfer direction.
The free time between a STOP and the next START condition is built into the hardware that generates the
START cycle. Depending on the relative frequencies of the system clock and the I2C_SCL period, the
MCF5282 and MCF5216 ColdFire Microcontroller User鈥檚 Manual, Rev. 3
鐩搁棞(gu膩n)PDF璩囨枡
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MCF5280CVM80J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU V2CORE NO FLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF5281CVF66 鍔熻兘鎻忚堪:IC MPU 32BIT 66MHZ 256-BGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:MCF528x 妯�(bi膩o)婧�(zh菙n)鍖呰:250 绯诲垪:56F8xxx 鏍稿績铏曠悊鍣�:56800E 鑺珨灏哄:16-浣� 閫熷害:60MHz 閫i€氭€�:CAN锛孲CI锛孲PI 澶栧湇瑷�(sh猫)鍌�:POR锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):21 绋嬪簭瀛樺劜鍣ㄥ閲�:40KB锛�20K x 16锛� 绋嬪簭瀛樺劜鍣ㄩ鍨�:闁冨瓨 EEPROM 澶у皬:- RAM 瀹归噺:6K x 16 闆诲 - 闆绘簮 (Vcc/Vdd):2.25 V ~ 3.6 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 6x12b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:48-LQFP 鍖呰:鎵樼洡 閰嶇敤:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
MCF5281CVF80 鍔熻兘鎻忚堪:IC MPU 32BIT COLDF 256-MAPBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:MCF528x 妯�(bi膩o)婧�(zh菙n)鍖呰:250 绯诲垪:56F8xxx 鏍稿績铏曠悊鍣�:56800E 鑺珨灏哄:16-浣� 閫熷害:60MHz 閫i€氭€�:CAN锛孲CI锛孲PI 澶栧湇瑷�(sh猫)鍌�:POR锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):21 绋嬪簭瀛樺劜鍣ㄥ閲�:40KB锛�20K x 16锛� 绋嬪簭瀛樺劜鍣ㄩ鍨�:闁冨瓨 EEPROM 澶у皬:- RAM 瀹归噺:6K x 16 闆诲 - 闆绘簮 (Vcc/Vdd):2.25 V ~ 3.6 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 6x12b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:48-LQFP 鍖呰:鎵樼洡 閰嶇敤:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
MCF5281CVM66 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU MCF5281 V2CORE 256KFLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF5281CVM66J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU V2CORE 256K FLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT