I2C Interface Freescale Semiconductor 24-7 24.3 Functional Description
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MCF5280CVM80J
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 403/766闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MPU RISC 80MHZ 256-MAPBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� MCF528x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 80MHz
閫i€氭€э細 CAN锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 DMA锛孡VD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 150
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 ROMless
RAM 瀹归噺锛� 64K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 3.6 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 256-LBGA
鍖呰锛� 鎵樼洡
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I2C Interface
Freescale Semiconductor
24-7
24.3
Functional Description
The I2C module uses a serial data line (I2C_SDA) and a serial clock line (I2C_SCL) for data transfer. For
I2C compliance, all devices connected to these two signals must have open drain or open collector outputs.
The logic AND function is exercised on both lines with external pull-up resistors.
Out of reset, the I2C default state is as a slave receiver. Therefore, when not programmed to be a master or
responding to a slave transmit address, the I2C module should return to the default slave receiver state. See
Normally, a standard communication is composed of four parts: START signal, slave address transmission,
data transfer, and STOP signal. These are discussed in the following sections.
24.3.1
START Signal
When no other device is bus master (I2C_SCL and I2C_SDA lines are at logic high), a device can initiate
communication by sending a START signal (see A in Figure 24-7). A START signal is defined as a
high-to-low transition of I2C_SDA while I2C_SCL is high. This signal denotes the beginning of a data
transfer (each data transfer can be several bytes long) and awakens all slaves.
IPSBAR
Offset:
0x00_0310 (I2DR)
Access: User read/write
76543210
R
DATA
W
Reset:
00
000000
Figure 24-6. I2C Data I/O Register (I2DR)
Table 24-6. I2DR Field Description
Field
Description
7鈥�0
DATA
I2C data. When data is written to this register in master transmit mode, a data transfer is initiated. The most significant
bit is sent first. In master receive mode, reading this register initiates the reception of the next byte of data. In slave
mode, the same functions are available after an address match has occurred.
Note: In master transmit mode, the first byte of data written to I2DR following assertion of I2CR[MSTA] is used for
the address transfer and should comprise the calling address (in position D7鈥揇1) concatenated with the
required R/W bit (in position D0). This bit (D0) is not automatically appended by the hardware, software must
provide the appropriate R/W bit.
Note: I2CR[MSTA] generates a start when a master does not already own the bus. I2CR[RSTA] generates a start
(restart) without the master first issuing a stop (i.e., the master already owns the bus). To start the read of data,
a dummy read to this register starts the read process from the slave. The next read of the I2DR register
contains the actual data.
MCF5282 and MCF5216 ColdFire Microcontroller User鈥檚 Manual, Rev. 3
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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VE-2WX-CV-S CONVERTER MOD DC/DC 5.2V 150W
VE-2W0-CV-S CONVERTER MOD DC/DC 5V 150W
VE-21H-CV-S CONVERTER MOD DC/DC 52V 150W
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鍙冩暩(sh霉)鎻忚堪
MCF5281CVF66 鍔熻兘鎻忚堪:IC MPU 32BIT 66MHZ 256-BGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:MCF528x 妯�(bi膩o)婧�(zh菙n)鍖呰:250 绯诲垪:56F8xxx 鏍稿績铏曠悊鍣�:56800E 鑺珨灏哄:16-浣� 閫熷害:60MHz 閫i€氭€�:CAN锛孲CI锛孲PI 澶栧湇瑷�(sh猫)鍌�:POR锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):21 绋嬪簭瀛樺劜鍣ㄥ閲�:40KB锛�20K x 16锛� 绋嬪簭瀛樺劜鍣ㄩ鍨�:闁冨瓨 EEPROM 澶у皬:- RAM 瀹归噺:6K x 16 闆诲 - 闆绘簮 (Vcc/Vdd):2.25 V ~ 3.6 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 6x12b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:48-LQFP 鍖呰:鎵樼洡 閰嶇敤:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
MCF5281CVF80 鍔熻兘鎻忚堪:IC MPU 32BIT COLDF 256-MAPBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:MCF528x 妯�(bi膩o)婧�(zh菙n)鍖呰:250 绯诲垪:56F8xxx 鏍稿績铏曠悊鍣�:56800E 鑺珨灏哄:16-浣� 閫熷害:60MHz 閫i€氭€�:CAN锛孲CI锛孲PI 澶栧湇瑷�(sh猫)鍌�:POR锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):21 绋嬪簭瀛樺劜鍣ㄥ閲�:40KB锛�20K x 16锛� 绋嬪簭瀛樺劜鍣ㄩ鍨�:闁冨瓨 EEPROM 澶у皬:- RAM 瀹归噺:6K x 16 闆诲 - 闆绘簮 (Vcc/Vdd):2.25 V ~ 3.6 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 6x12b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:48-LQFP 鍖呰:鎵樼洡 閰嶇敤:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
MCF5281CVM66 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU MCF5281 V2CORE 256KFLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF5281CVM66J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU V2CORE 256K FLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF5281CVM80 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU MCF5281 V2CORE 256KFLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT