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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MCF5281CVM66J
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 199/766闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MPU 256K FLASH 256MAPBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� MCF528x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 66MHz
閫i€氭€э細 CAN锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 DMA锛孡VD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 150
绋嬪簭瀛樺劜鍣ㄥ閲忥細 256KB锛�256K x 8锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 64K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 3.6 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 256-LBGA
鍖呰锛� 鎵樼洡
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29闋�绗�730闋�绗�731闋�绗�732闋�绗�733闋�绗�734闋�绗�735闋�绗�736闋�绗�737闋�绗�738闋�绗�739闋�绗�740闋�绗�741闋�绗�742闋�绗�743闋�绗�744闋�绗�745闋�绗�746闋�绗�747闋�绗�748闋�绗�749闋�绗�750闋�绗�751闋�绗�752闋�绗�753闋�绗�754闋�绗�755闋�绗�756闋�绗�757闋�绗�758闋�绗�759闋�绗�760闋�绗�761闋�绗�762闋�绗�763闋�绗�764闋�绗�765闋�绗�766闋�
Synchronous DRAM Controller Module
15-6
Freescale Semiconductor
15.2.2.2
DRAM Address and Control Registers (DACR0/DACR1)
The DACRn registers, shown in Figure 15-3, contain the base address compare value and the control bits
for memory blocks 0 and 1 of the SDRAM controller. Address and timing are also controlled by bits in
DACRn.
Table 15-5 describes DACRn fields.
31
18 17 16
15
14 13 12 11 10 9
8
7
6
5
4
3
2
0
Field
BA
鈥�
RE 鈥� CASL 鈥�
CBM
鈥� IMRS
PS
IP
鈥�
Reset
Uninitialized
0
Uninitialized
0
Uninitialized
R/W
Address
IPSBAR+0x048 (DACR0); 0x050 (DACR1)
Figure 15-3. DRAM Address and Control Register (DACRn)
Table 15-5. DACRn Field Descriptions
Bit
Name
Description
31鈥�18
BA
Base address register. With DCMR[BAM], determines the address range in which the associated
DRAM block is located. Each BA bit is compared with the corresponding address of the current bus
cycle. If all unmasked bits match, the address hits in the associated DRAM block. BA functions the
same as in asynchronous operation.
17鈥�16
鈥�
Reserved, should be cleared.
15
RE
Refresh enable. Determines when the DRAM controller generates a refresh cycle to the DRAM block.
0 Do not refresh associated DRAM block
1 Refresh associated DRAM block
14
鈥�
Reserved, should be cleared.
13鈥�12
CASL CAS latency. Affects the following SDRAM timing specifications. Timing nomenclature varies with
manufacturers. Refer to the SDRAM specification for the appropriate timing nomenclature:
Parameter
Number of Bus Clocks
CASL= 00 CASL = 01 CASL= 10
CASL= 11
t
RCD鈥擲RAS assertion to SCAS assertion
1
2
3
t
CASL鈥擲CAS assertion to data out
1
2
3
t
RAS鈥�ACTV command to precharge command
2
4
6
t
RP鈥擯recharge command to ACTV command
1
2
3
t
RWL
,tRDL鈥擫ast data input to precharge
command
11
1
t
EP鈥擫ast data out to precharge command
1
11
鈥�
Reserved, should be cleared.
MCF5282 and MCF5216 ColdFire Microcontroller User鈥檚 Manual, Rev. 3
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
MCF5281CVM80 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU MCF5281 V2CORE 256KFLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF5282 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:CodeWarrior Development Studio for ColdFire銏� Architectures
MCF5282CVF66 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU MCF5282 V2CORE 512KFLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF5282CVF66J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU V2CORE 512K FLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF5282CVF80 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU MCF5282 V2CORE 512KFLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT