The USRn registers show the status of the transmitter, the receiv" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MCF5281CVM80
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 366/766闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MPU 32BIT COLDF 256-MAPBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� MCF528x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 80MHz
閫i€氭€э細 CAN锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 DMA锛孡VD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 142
绋嬪簭瀛樺劜鍣ㄥ閲忥細 256KB锛�256K x 8锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 64K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 3.6 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 256-LBGA
鍖呰锛� 鎵樼洡
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UART Modules
23-8
Freescale Semiconductor
23.3.3
UART Status Registers (USRn)
The USRn registers show the status of the transmitter, the receiver, and the FIFO.
IPSBAR
Offset:
0x00_0204 (USR0)
0x00_0244 (USR1)
0x00_0284 (USR2)
Access: User read-only
76543210
R
RB
FE
PE
OE
TXEMP
TXRDY
FFULL
RXRDY
W
Reset:
000
00000
Figure 23-5. UART Status Registers (USRn)
Table 23-5. USRn Field Descriptions
Field
Description
7
RB
Received break. The received break circuit detects breaks originating in the middle of a received character. However,
a break in the middle of a character must persist until the end of the next detected character time.
0 No break was received.
1 An all-zero character of the programmed length was received without a stop bit. Only a single FIFO position is
occupied when a break is received. Further entries to the FIFO are inhibited until URXDn returns to the high state
for at least one-half bit time, which equals two successive edges of the UART clock. RB is valid only when RXRDY
is set.
6
FE
Framing error.
0 No framing error occurred.
1 No stop bit was detected when the corresponding data character in the FIFO was received. The stop-bit check
occurs in the middle of the first stop-bit position. FE is valid only when RXRDY is set.
5
PE
Parity error. Valid only if RXRDY is set.
0 No parity error occurred.
1 If UMR1n[PM] equals 0x (with parity or force parity), the corresponding character in the FIFO was received with
incorrect parity. If UMR1n[PM] equals 11 (multidrop), PE stores the received address or data (A/D) bit. PE is valid
only when RXRDY is set.
4
OE
Overrun error. Indicates whether an overrun occurs.
0 No overrun occurred.
1 One or more characters in the received data stream have been lost. OE is set upon receipt of a new character
when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position. When this
occurs, the character in the receiver shift register and its break detect, framing error status, and parity error, if any,
are lost. The RESET ERROR STATUS command in UCRn clears OE.
3
TEMP
Transmitter empty.
0 The transmit buffer is not empty. A character is shifted out, or the transmitter is disabled. The transmitter is
enabled/disabled by programming UCRn[TC].
1 The transmitter has underrun (the transmitter holding register and transmitter shift registers are empty). This bit
is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding
register awaiting transmission.
2
TXRDY
Transmitter ready.
0 The CPU loaded the transmitter holding register, or the transmitter is disabled.
1 The transmitter holding register is empty and ready for a character. TXRDY is set when a character is sent to the
transmitter shift register or when the transmitter is first enabled. If the transmitter is disabled, characters loaded
into the transmitter holding register are not sent.
MCF5282 and MCF5216 ColdFire Microcontroller User鈥檚 Manual, Rev. 3
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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MCF5282CVF66 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU MCF5282 V2CORE 512KFLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF5282CVF66J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU V2CORE 512K FLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF5282CVF80 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU MCF5282 V2CORE 512KFLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF5282CVF80J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU V2CORE 512K FLASH RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT