MCF532x ColdFire Microprocessor Data Sheet, Rev. 5 Pin Assignments and Reset Sta" />
參數(shù)資料
型號(hào): MCF5329CVM240
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 4/50頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT 240MHZ 256-MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: MCF532x
核心處理器: Coldfire V3
芯體尺寸: 32-位
速度: 240MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,LCD,PWM,WDT
輸入/輸出數(shù): 94
程序存儲(chǔ)器類型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.4 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 托盤
MCF532x ColdFire Microprocessor Data Sheet, Rev. 5
Pin Assignments and Reset States
Freescale Semiconductor
12
PST[3:0]
O
EVDD
N8, P8, L9,
M9
R10, T10,
R11, T11
R10, T10,
R11, T11
Test
TEST7
I
EVDD
E10
A16
PLL_TEST8
I
EVDD
N13
Power Supplies
EVDD
E6, E7,
F5–F7, H9,
J8, J9, K8,
K9, K11
E8, F5–F8,
G5, G6, H5,
H6, J11,
K11, K12,
L9–L11, M9,
M10
E8, F5–F8,
G5, G6, H5,
H6, J11,
K11, K12,
L9–L11, M9,
M10
IVDD
E5, K5, K10,
J10
E5, G12, M5,
M11, M12
E5, G12, M5,
M11, M12
PLL_VDD
H10
J12
SD_VDD
E8, E9,
F8–F10,
J5–J7, K7
E9, F9–F11,
G11, H11,
J5, J6, K5,
K6, L5–L8,
M6, M7
E9, F9–F11,
G11, H11,
J5, J6, K5,
K6, L5–L8,
M6, M7
USB_VDD
G10
L14
VSS
G6–G9,
H6–H8, P9
G7–G10,
H7–H10,
J7–10,
K7–K10,
L12, L13
G7–G10,
H7–H10,
J7–10,
K7–K10,
L12, L13
PLL_VSS
H11
K13
USB_VSS
H12
M14
1 Refers to pin’s primary function.
2 Pull-up enabled internally on this signal for this mode.
3 The SDRAM functions of these signals are not programmable by the user. They are dynamically switched by the processor
when accessing SDRAM memory space and are included here for completeness.
4 Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating
the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.
5 GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate
functions.
6 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for
assigning these pins.
7 Pull-down enabled internally on this signal for this mode.
8 Must be left floating for proper operation of the PLL.
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
Signal Name
GPIO
Alternate 1
Alternate 2
Di
r.
1
Vo
lt
a
g
e
Domain
MCF5327
196
MAPBGA
MCF5328
256
MAPBGA
MCF53281
MCF5329
256
MAPBGA
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