參數(shù)資料
型號(hào): MCF54417CMJ250
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROPROCESSOR, PBGA256
封裝: 12 X 12 MM, ROHS COMPLAINT, MAPBGA-256
文件頁(yè)數(shù): 35/60頁(yè)
文件大?。?/td> 1107K
代理商: MCF54417CMJ250
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 6
Preliminary—Subject to Change Without Notice
Electrical characteristics
Freescale Semiconductor
40
4.16.2.2
Cards with active-low reset
The sequence of reset for this kind of card is as follows (see Figure 23):
1. After powerup, the clock signal is enabled on SIM_CLK (time T0)
2. After 200 clock cycles, RX must be high.
3. SIM_RST must remain low for at least 40,000 clock cycles after T0 (no response is to be received on RX during those
40,000 clock cycles)
4. SIM_RST is set high (time T1)
5. SIM_RST must remain high for at least 40,000 clock cycles after T1 and a response must be received on RX between
400 and 40,000 clock cycles after T1.
Figure 23. Active-low-reset card reset sequence
4.16.3
Power-down sequence
Power down sequence for SIM interface is as follows:
1. SIM_PD port detects the removal of the SIM card
2. SIM_RST goes low
3. SIM_CLK goes low
4. SIM_TX goes low
5. SIM_VEN goes low
Each of these steps is completed in one CKIL period (usually 32 kHz). Power-down may be started in response to a
card-removal detection or launched by the processor. Figure 24 and Table 23 show the usual timing requirements for this
sequence, with Fckil = CKIL frequency value.
SIM_VEN
SIM_CLK
SIM_RX
2
T0
1
Response
SIM_RST
T1
1
2
< 200 clock cycles
< 40,000 clock cycles
400 clock cycles <
3
400,000 clock cycles <
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參數(shù)描述
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