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參數(shù)資料
| 型號： | MCF5475VR200 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 11/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT COLDF 388-PBGA |
| 標準包裝： | 40 |
| 系列： | MCF547x |
| 核心處理器： | Coldfire V4E |
| 芯體尺寸： | 32-位 |
| 速度： | 200MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，SPI，UART/USART，USB |
| 外圍設備： | DMA，PWM，WDT |
| 輸入/輸出數(shù)： | 99 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.43 V ~ 1.58 V |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 388-BBGA |
| 包裝： | 托盤 |
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SDRAM Bus
MCF547x ColdFire Microprocessor, Rev. 4
Freescale Semiconductor
19
DD13
DQS input read preamble width (tRPRE)
0.9
1.1
SDCLK
DD14
DQS input read postamble width (tRPST)
0.4
0.6
SDCLK
DD15
DQS output write preamble width (tWPRE)0.25
—
SDCLK
DD16
DQS output write postamble width (tWPST)
0.4
0.6
SDCLK
1
DDR memories typically have a minimum speed specification of 83 MHz. Check memory component specifications to verify.
2 The frequency of operation is 2x or 4x the CLKIN frequency of operation. The MCF547X supports a single external
reference clock (CLKIN). This signal defines the frequency of operation for FlexBus and PCI, but SDRAM clock operates at
the same frequency as the internal bus clock. Please see the reset configuration signals description in the “Signal
Descriptions” chapter within the MCF547x Reference Manual.
3 SDCLK is one memory clock in (ns).
4 Pulse width high plus pulse width low cannot exceed max clock period.
5 Pulse width high plus pulse width low cannot exceed max clock period.
6 Command output valid should be 1/2 the memory bus clock (SDCLK) plus some minor adjustments for process,
temperature, and voltage variations.
7 This specification relates to the required input setup time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3,
SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0.
8 The first data beat is valid before the first rising edge of SDDQS and after the SDDQS write preamble. The remaining data
beats is valid for each subsequent SDDQS edge.
9 This specification relates to the required hold time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3,
SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0.
10 Data input skew is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the last data
line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing
or other factors).
11 Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data
line becomes invalid.
Table 13. DDR Timing Specifications (continued)
Symbol
Characteristic
Min
Max
Unit
Notes
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MCF5475VR266 | 功能描述:微處理器 - MPU MCF547X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5475ZP200 | 功能描述:微處理器 - MPU MCF547X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5475ZP266 | 功能描述:微處理器 - MPU MCF547X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF547X | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF547x ColdFire㈢ Microprocessor |
| MCF547X_07 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF547x ColdFire㈢ Microprocessor |
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