Technical Data
MC68HC908MR8 — Rev 4.1
82
Central Processor Unit (CPU)
Freescale Semiconductor
Central Processor Unit (CPU)
CMP #opr
CMP opr
CMP opr,X
CMP ,X
CMP opr,SP
Compare A with M
(A) – (M)
––
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A1
B1
C1
D1
E1
F1
9EE1
9ED1
ii
dd
hh ll
ee ff
ff
ee ff
2
3
4
3
2
4
5
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
Complement (One’s Complement)
M
← (M) = $FF – (M)
A
← (A) = $FF – (M)
X
← (X) = $FF – (M)
M
← (M) = $FF – (M)
M
← (M) = $FF – (M)
M
← (M) = $FF – (M)
0–– 1
DIR
INH
IX1
IX
SP1
33
43
53
63
73
9E63
dd
ff
4
1
4
3
5
CPHX #opr
CPHX opr
Compare H:X with M
(H:X) – (M:M + 1)
–– IMM
DIR
65
75
ii ii+1
dd
3
4
CPX #opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,SP
Compare X with M
(X) – (M)
––
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A3
B3
C3
D3
E3
F3
9EE3
9ED3
ii
dd
hh ll
ee ff
ff
ee ff
2
3
4
3
2
4
5
DAA
Decimal Adjust A
(A)10
U– – INH
72
2
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
Decrement and Branch if Not Zero
A
← (A) – 1 or M ← (M) – 1 or X ←(X) – 1
PC
← (PC) + 3 + rel ? (result) 0
PC
← (PC) + 2 + rel ? (result) 0
PC
← (PC) + 2 + rel ? (result) 0
PC
← (PC) + 3 + rel ? (result) 0
PC
← (PC) + 2 + rel ? (result) 0
PC
← (PC) + 4 + rel ? (result) 0
––– –––
DIR
INH
IX1
IX
SP1
3B
4B
5B
6B
7B
9E6B
dd rr
rr
ff rr
rr
ff rr
5
3
5
4
6
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
Decrement
M
← M) – 1
A
← A) – 1
X
← (X) – 1
M
← (M) – 1
M
← (M) – 1
M
← (M) – 1
–– –
DIR
INH
IX1
IX
SP1
3A
4A
5A
6A
7A
9E6A
dd
ff
4
1
4
3
5
DIV
Divide
A
← (H:A)/(X)
H
← Remainder
––– – INH
52
7
EOR #opr
EOR opr
EOR opr,X
EOR ,X
EOR opr,SP
Exclusive OR M with A
A
← (A M)
0–– –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A8
B8
C8
D8
E8
F8
9EE8
9ED8
ii
dd
hh ll
ee ff
ff
ee ff
2
3
4
3
2
4
5
Table 6-1. Instruction Set Summary (Sheet 4 of 8)
Source
Form
Operation
Description
Effect on CCR
Address
Mo
de
Opcode
Operand
Cycl
es
VH I N Z C