參數(shù)資料
型號(hào): MCHRC705KJ1CPE
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 60/108頁(yè)
文件大?。?/td> 0K
描述: IC MCU 1.2K 4MHZ OTP 16-DIP
標(biāo)準(zhǔn)包裝: 25
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 10
程序存儲(chǔ)器容量: 1.2KB(1.2K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-DIP(0.300",7.62mm)
包裝: 管件
Timing
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
55
The STOP and WAIT instructions set the IRQE bit so that an external interrupt can bring the MCU out of
these low-power modes. In addition, reset sets the I bit which masks all interrupt sources.
5.5 Timing
Figure 5-5. External Interrupt Timing
Table 5-1. External Interrupt Timing (VDD = 5.0 Vdc)
(1)
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to + 85°C, unless otherwise noted.
Characteristic
Symbol
Min
Max
Unit
IRQ Interrupt Pulse Width Low (Edge-Triggered)
tILIH
1.5
tcyc
(2)
2. tcyc = 1/fOP; fOP = fOSC/2.
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered)
tILIH
1.5
Note(3)
3. The minimum tILIL should not be less than the number of interrupt service routine cycles plus 19 tcyc.
tcyc
PA0–PA3 Interrupt Pulse Width High (Edge-Triggered)
tILIL
1.5
tcyc
PA0–PA3 Interrupt Pulse Width High (Edge- and Level-Triggered)
tILIH
1.5
Note(3)
tcyc
Table 5-2. External Interrupt Timing (VDD = 3.3 Vdc)
(1)
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to + 85°C, unless otherwise noted.
Characteristic
Symbol
Min
Max
Unit
IRQ Interrupt Pulse Width Low (Edge-Triggered)
tILIH
1.5
tcyc
(2)
2. tcyc = 1/fOP; fOP = fOSC/2.
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered)
tILIH
1.5
Note(3)
3. The minimum tILIL should not be less than the number of interrupt service routine cycles plus 19 tcyc.
tcyc
PA0–PA3 Interrupt Pulse Width High (Edge-Triggered)
tILIL
1.5
tcyc
PA0–PA3 Interrupt Pulse Width High (Edge- and Level-Triggered)
tILIH
1.5
Note(3)
tcyc
IRQ (INTERNAL)
tILIH
tILIL
tILIH
IRQ/VPP PIN
IRQ1
IRQn
.
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