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參數(shù)資料
| 型號(hào)： | MCIMX511DVK8C |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA625 |
| 封裝： | 13 X 13 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-625 |
| 文件頁(yè)數(shù)： | 174/184頁(yè) |
| 文件大小： | 3644K |
| 代理商： | MCIMX511DVK8C |
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Features
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1
Freescale Semiconductor
9
Preliminary—Subject to Change Without Notice
RTIC
Real Time
Integrity
Checker
Security
Protecting read-only data from modification is one of the basic elements in
trusted platforms. The Run-Time Integrity Checker v3 (RTICv3) module, is a data
monitoring device responsible for ensuring that memory content is not corrupted
during program execution. The RTICv3 mechanism periodically checks the
integrity of code or data sections during normal OS run-time execution without
interfering with normal operation. The RTICv3’s purpose is to ensure the integrity
of the peripheral memory contents, protect against unauthorized external
memory elements replacement, and assist with boot authentication.
SAHARA Lite SAHARA
security
accelerator
Lite
Security
SAHARA (Symmetric/Asymmetric Hashing and Random Accelerator) is a
security co-processor. It implements symmetric encryption algorithms, (AES,
DES, 3DES, and RC4), public key algorithms, hashing algorithms (MD5, SHA-1,
SHA-224, and SHA-256), and a hardware random number generator. It has a
slave IP bus interface for the host to write configuration and command
information, and to read status information. It also has a DMA controller, with an
AHB bus interface, to reduce the burden on the host to move the required data
to and from memory.
SCC
Security
Controller
Security
The Security Controller is a security assurance hardware module designed to
safely hold sensitive data such as encryption keys, digital right management
(DRM) keys, passwords, and biometrics reference data. The SCC monitors the
system’s alert signal to determine if the data paths to and from it are
secure—that is, cannot be accessed from outside of the defined security
perimeter. If not, it erases all sensitive data on its internal RAM. The SCC also
features a Key Encryption Module (KEM) that allows non-volatile (external
memory) storage of any sensitive data that is temporarily not in use. The KEM
utilizes a device-specific hidden secret key and a symmetric cryptographic
algorithm to transform the sensitive data into encrypted data.
SDMA
Smart Direct
Memory
Access
System
Control
Peripherals
The SDMA is multi-channel flexible DMA engine. It helps in maximizing system
performance by off loading various cores in dynamic data routing.
The SDMA features list is as follows:
Powered by a 16-bit instruction-set micro-RISC engine
Multi-channel DMA supports up to 32 time-division multiplexed DMA channels
48 events with total flexibility to trigger any combination of channels
Memory accesses including linear, FIFO, and 2D addressing
Shared peripherals between ARM Cortex A8 and SDMA
Very fast context-switching with two-level priority-based preemptive
multi-tasking
DMA units with auto-flush and prefetch capability
Flexible address management for DMA transfers (increment, decrement, and
no address changes on source and destination address)
DMA ports can handle unit-directional and bi-directional flows (copy mode)
Up to 8-word buffer for configurable burst transfers for EMI
Support of byte-swapping and CRC calculations
A library of scripts and API are available
SIM
Subscriber
Identity
Module
Interface
Connectivity
Peripherals
The SIM is an asynchronous interface with additional features for allowing
communication with Smart Cards conforming to the ISO 7816 specification. The
SIM is designed to facilitate communication to SIM cards or pre-paid phone
cards.
Table 2. i.MX51 Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MCIMX512DVK8C,
MCIMX513DVK8C,
MCIMX515DVK8C,
and
MCIMX511DVK8C.
相關(guān)PDF資料 |
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|---|---|
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| MCIMX537CVV8C | 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529 |
| MCM16Y1BACFT16 | 16-BIT, MROM, MICROCONTROLLER, PQFP160 |
| MCM16Y1BGCFT16 | 16-BIT, MROM, MICROCONTROLLER, PQFP160 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCIMX512CJM6C | 功能描述:處理器 - 專門應(yīng)用 iMX512 App Processor RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX512CJM6CR2 | 功能描述:處理器 - 專門應(yīng)用 i.MX51 32bit 800 MHz RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX512CVM6C | 制造商:Freescale Semiconductor 功能描述:ELVIS 3.0 - Bulk |
| MCIMX512DJM8C | 功能描述:處理器 - 專門應(yīng)用 iMX512 App Processor Extended Temp RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX512DJM8CR2 | 功能描述:處理器 - 專門應(yīng)用 i.MX51 32bit 800 MHz RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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