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參數(shù)資料
| 型號： | MCIMX512DVK8C |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA625 |
| 封裝： | 13 X 13 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-625 |
| 文件頁數(shù)： | 2/184頁 |
| 文件大?。?/td> | 3644K |
| 代理商： | MCIMX512DVK8C |
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i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1
10
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Features
SJC
Secure JTAG
Interface
System
Control
Peripherals
JTAG manipulation is a known hacker’s method of executing unauthorized
program code, getting control over secure applications, and running code in
privileged modes. The JTAG port provides a debug access to several hardware
blocks including the ARM processor and the system bus.
The JTAG port must be accessible during platform initial laboratory bring-up,
manufacturing tests and troubleshooting, as well as for software debugging by
authorized entities. However, in order to properly secure the system,
unauthorized JTAG usage should be strictly forbidden.
In order to prevent JTAG manipulation while allowing access for manufacturing
tests and software debugging, the i.MX51 processor incorporates a mechanism
for regulating JTAG access. The i.MX51Secure JTAG Controller provides four
different JTAG security modes that can be selected via e-fuse configuration.
SPBA
Shared
Peripheral
Bus Arbiter
System
Control
Peripherals
SPBA (Shared Peripheral Bus Arbiter) is a two-to-one IP bus interface (IP bus)
arbiter.
SPDIF
Sony Philips
Digital
Interface
Multimedia
Peripherals
A standard digital audio transmission protocol developed jointly by the Sony and
Philips corporations. Only the transmitter functionality is supported.
SRTC
Secure Real
Time Clock
Security
The SRTC incorporates a special System State Retention Register (SSRR) that
stores system parameters during system shutdown modes. This register and all
SRTC counters are powered by dedicated supply rail NVCC_SRTC_POW. The
NVCC_SRTC_POW can be energized even if all other supply rails are shut
down. This register is helpful for storing warm boot parameters. The SSRR also
stores the system security state. In case of a security violation, the SSRR mark
the event (security violation indication).
SSI-1
I2S/SSI/AC97
Interface
Connectivity
Peripherals
The SSI is a full-duplex synchronous interface used on the i.MX51 processor to
provide connectivity with off-chip audio peripherals. The SSI supports a wide
variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up to
24 bits per word), and clock/frame sync options.
Each SSI has two pairs of 8x24 FIFOs and hardware support for an external
DMA controller in order to minimize its impact on system performance. The
second pair of FIFOs provides hardware interleaving of a second audio stream,
which reduces CPU overhead in use cases where two timeslots are being used
simultaneously.
SSI-2
SSI-3
TVE
TV Encoder
Multimedia
The TVE is implemented in conjunction with the Image Processing Unit (IPU)
allowing handheld devices to display captured still images and
video directly on a TV or LCD projector. It supports the following analog video
outputs: composite, S-video, and component video up to HD720p/1080i.
TZIC
TrustZone
Aware
Interrupt
Controller
ARM/Control
The TrustZone Interrupt Controller (TZIC) collects interrupt requests from all
i.MX51A sources and routes them to the ARM core. Each interrupt can be
configured as a normal or a secure interrupt. Software Force Registers and
software Priority Masking are also supported.
Table 2. i.MX51 Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MCIMX512DVK8C,
MCIMX513DVK8C,
MCIMX515DVK8C,
and
MCIMX511DVK8C.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCIMX513CJM6C | 功能描述:處理器 - 專門應(yīng)用 iMX513 App Processor RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX513CJM6CR2 | 功能描述:處理器 - 專門應(yīng)用 i.MX51 32bit 800 MHz RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX513DJM8C | 功能描述:處理器 - 專門應(yīng)用 iMX513 App Processor Extended Temp RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX513DJM8CR2 | 功能描述:處理器 - 專門應(yīng)用 i.MX51 32bit 800 MHz RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX514AJM6C | 功能描述:處理器 - 專門應(yīng)用 ELVIS 3.0 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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