參數(shù)資料
型號(hào): MCIMX515DVK8C
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 159/202頁(yè)
文件大小: 0K
描述: IC MPU I.MX51 527MABGA
標(biāo)準(zhǔn)包裝: 160
系列: i.MX51
核心處理器: ARM? Cortex?-A8
芯體尺寸: 32-位
速度: 800MHz
連通性: 1 線,EBI/EMI,以太網(wǎng),I²C,IrDA,MMC,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 128
程序存儲(chǔ)器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 0.8 V ~ 1.15 V
振蕩器型: 外部
工作溫度: -20°C ~ 85°C
封裝/外殼: 527-LFBGA
包裝: 托盤(pán)
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i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
6
Freescale Semiconductor
Features
EMI
External
Memory
Interface
Connectivity
Peripherals
The EMI is an external and internal memory interface. It performs arbitration
between multi-AXI masters to multi-memory controllers, divided into four major
channels: fast memories (Mobile DDR, DDR2) channel, slow memories
(NOR-FLASH/PSRAM/NAND-FLASH and so on) channel, internal memory
(RAM, ROM) channel and graphical memory (GMEM) Channel.
In order to increase the bandwidth performance, the EMI separates the buffering
and the arbitration between different channels so parallel accesses can occur.
By separating the channels, slow accesses do not interfere with fast accesses.
EMI features:
64-bit and 32-bit AXI ports
Enhanced arbitration scheme for fast channel, including dynamic master
priority, and taking into account which pages are open or closed and what
type (Read or Write) was the last access
Flexible bank interleaving
Supports 16/32-bit Mobile DDR up to 200 MHz SDCLK (mDDR400)
Supports 16/32-bit (Non-Mobile) DDR2 up to 200 MHz SDCLK (DDR2-400)
Supports up to 2 Gbit Mobile DDR memories
Supports 16-bit (in muxed mode only) PSRAM memories (sync and async
operating modes), at slow frequency, for debugging purposes
Supports 32-bit NOR-Flash memories (only in muxed mode), at slow
frequencies for debugging purposes
Supports 4/8-ECC, page sizes of 512 Bytes, 2 Kbytes and 4 Kbytes
NAND-Flash (including MLC)
Multiple chip selects
Enhanced Mobile DDR memory controller, supporting access latency hiding
Supports watermarking for security (Internal and external memories)
Supports Samsung OneNAND
(only in muxed I/O mode)
EPIT-1
EPIT-2
Enhanced
Periodic
Interrupt
Timer
Peripherals
Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT is
enabled by software. It is capable of providing precise interrupts at regular
intervals with minimal processor intervention. It has a 12-bit prescaler for division
of input clock frequency to get the required time setting for the interrupts to occur,
and counter values can be programmed on the fly.
eSDHC-1
eSDHC-2
eSDHC-3
Enhanced
Multi-Media
Card/
Secure Digital
Host
Controller
Connectivity
Peripherals
The features of the eSDHC module, when serving as host, include the following:
Conforms to SD Host Controller Standard Specification version 2.0
Compatible with the MMC System Specification version 4.2
Compatible with the SD Memory Card Specification version 2.0
Compatible with the SDIO Card Specification version 1.2
Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD
Combo, MMC and MMC RS cards
Configurable to work in one of the following modes:
—SD/SDIO 1-bit, 4-bit
—MMC 1-bit, 4-bit, 8-bit
Full-/high-speed mode
Host clock frequency variable between 32 kHz to 52 MHz
Up to 200 Mbps data transfer for SD/SDIO cards using four parallel data lines
Up to 416 Mbps data transfer for MMC cards using eight parallel data lines
Table 2. i.MX51 Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
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