MOTOROLA
OVERVIEW
M68HC16 Z SERIES
3-2
USER’S MANUAL
3.1.4 Masked ROM Module (MRM) — (MC68HC16Z2/Z3 Only)
8-Kbyte array, accessible as bytes or words
User-selectable default base address
User-selectable bootstrap ROM function
User-selectable ROM verification code
3.1.5 Analog-to-Digital Converter (ADC)
Eight channels, eight result registers
Eight automated modes
Three result alignment modes
3.1.6 Queued Serial Module (QSM)
Enhanced serial communication interface
Queued serial peripheral interface
One 8-bit dual function port
3.1.7 Multichannel Communication Interface (MCCI) — (MC68HC16Z4/CKZ4 Only)
Two channels of enhanced SCI (UART)
One channel of SPI
3.1.8 General-Purpose Timer (GPT)
Two 16-bit free-running counters with prescaler
Three input capture channels
Four output compare channels
One input capture/output compare channel
One pulse accumulator/event counter input
Two pulse width modulation outputs
Optional external clock input
3.2 Intermodule Bus
The intermodule bus (IMB) is a standardized bus developed to facilitate the design of
modular microcontrollers. It contains circuitry that supports exception processing, ad-
dress space partitioning, multiple interrupt levels, and vectored interrupts. The stan-
dardized modules in M68HC16 Z-series MCUs communicate with one another via the
IMB. Although the full IMB supports 24 address and 16 data lines, M68HC16 Z-series
MCUs use only 20 address lines. ADDR[23:20] follow the state of ADDR19.
3.3 System Block Diagram and Pin Assignment Diagrams
Figure 3-1 is a functional diagram of the MC68HC16Z1/CKZ1/CMZ1 MCU. Refer to
functional diagram of the MC68HC16Z4/CKZ4 MCU. Although diagram blocks repre-
sent the relative size of the physical modules, there is not a one-to-one correspon-
dence between location and size of blocks in the diagram and location and size of
integrated-circuit modules.