參數(shù)資料
型號(hào): MCM6206DP20
廠商: MOTOROLA INC
元件分類(lèi): SRAM
英文描述: 32K x 8 Bit Fast Static RAM
中文描述: 32K X 8 STANDARD SRAM, 20 ns, PDIP28
封裝: 0.300 INCH, PLASTIC, DIP-28
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 162K
代理商: MCM6206DP20
MCM6206D
1
Motorola, Inc. 1994
32K x 8 Bit Fast Static RAM
The MCM6206D is fabricated using Motorola’s high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is avail-
able in plastic dual–in–line and plastic small–outline J–leaded packages.
Single 5 V
±
10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
Fast Access Times: 12, 15, 20, and 25 ns
Equal Address and Chip Enable Access Times
Output Enable (G) Feature for Increased System Flexibility and to
Eliminate Bus Contention Problems
Low Power Operation: 125 – 140 mA Maximum AC
Fully TTL Compatible — Three State Output
BLOCK DIAGRAM
A0
A2
A5
A10
A12
A13
A14
A1
A3
A4
A6
A7
A8
A9
A11
MEMORY MATRIX
256 ROWS x
128 x 8 COLUMNS
ROW
DECODER
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN DECODER
E
DQ0
DQ7
W
G
.
VCC
VSS
Order this document
by MCM6206D/D
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MCM6206D
A12
A7
A6
A5
A4
A3
A2
A1
A0
VSS
V
A13
A8
A9
CC
W
A11
G
DQ0
DQ6
A14
A10
DQ7
DQ4
DQ5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DQ1
DQ2
DQ3
E
A0 – A14
DQ0 – DQ7
W
. . . . . . . . . . . . . . . . . . . .
G
. . . . . . . . . . . . . . . . . . .
E
. . . . . . . . . . . . . . . . . . . . . .
VCC
. . . . . . . . . . .
VSS
. . . . . . . . . . . . . . . . . . . . . . .
Address Input
. . . . . . . . . . . . .
Data Input/Data Output
. . .
Write Enable
Output Enable
Chip Enable
Power Supply (+ 5 V)
Ground
P PACKAGE
300 MIL PLASTIC
CASE 710B–01
J PACKAGE
300 MIL SOJ
CASE 810B–03
PIN NAMES
REV 1
5/95
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