參數(shù)資料
型號: MCM6227BWJ25R2
廠商: MOTOROLA INC
元件分類: SRAM
英文描述: 1M x 1 Bit Static Random Access Memory
中文描述: 1M X 1 STANDARD SRAM, 25 ns, PDSO28
封裝: 0.400 INCH, SOJ-28
文件頁數(shù): 5/8頁
文件大?。?/td> 147K
代理商: MCM6227BWJ25R2
MCM6227B
5
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled, See Notes 1 and 2)
6227B–15
6227B–17
6227B–20
6227B–25
6227B–35
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
tAVWL
tAVWH
15
17
20
25
35
ns
3
Address Setup Time
0
0
0
0
0
ns
Address Valid to End of
Write
12
14
15
17
20
ns
Write Pulse Width
tWLWH,
tWLEH
12
14
15
17
20
ns
Data Valid to End of
Write
tDVWH
7
8
8
10
11
ns
Data Hold TIme
tWHDX
tWLQZ
0
0
0
0
0
ns
Write Low to Data
High–Z
6
7
7
8
8
ns
4, 5, 6
Write High to Output
Active
tWHQX
5
5
5
5
5
ns
4, 5, 6
Write Recovery Time
tWHAX
0
0
0
0
0
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-
tention conditions during read and write cycles.
3. All timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1b.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
(W Controlled See Notes 1 and 2)
tAVWH
tWLQZ
tWHAX
tDVWH
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
DATA VALID
HIGH–Z
HIGH–Z
tAVAV
tAVWL
tWLEH
tWLWH
tWHDX
tWHQX
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