參數(shù)資料
型號(hào): MCM6265CP25
廠商: MOTOROLA INC
元件分類: DRAM
英文描述: 8K x 9 Bit Fast Static RAM
中文描述: 8K X 9 STANDARD SRAM, 25 ns, PDIP28
封裝: 0.300 INCH, PLASTIC, DIP-28
文件頁數(shù): 1/8頁
文件大?。?/td> 177K
代理商: MCM6265CP25
MCM6265C
1
Motorola, Inc. 1994
8K x 9 Bit Fast Static RAM
The MCM6265C is fabricated using Motorola’s high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is avail-
able in plastic dual–in–line and plastic small–outline J–leaded packages.
Single 5 V
±
10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
Fast Access Times: 12, 15, 20, 25, and 35 ns
Equal Address and Chip Enable Access Times
Output Enable (G) Feature for Increased System Flexibility and to
Eliminate Bus Contention Problems
Low Power Operation: 110 – 150 mA Maximum AC
Fully TTL Compatible — Three State Output
ROW
DECODER
MEMORY MATRIX
256 ROWS x 32
x 9 COLUMNS
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN DECODER
DQ0
E1
E2
W
G
VCC
VSS
A1
DQ8
BLOCK DIAGRAM
A0
A6
A8 A12
A11
A10
A9
A7
A5
A4
A3
A2
Order this document
by MCM6265C/D
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MCM6265C
P PACKAGE
300 MIL PLASTIC
CASE 710B–01
A0 – A12
DQ0 – DQ8
W
. . . . . . . . . . . . . . . . . . . .
G
. . . . . . . . . . . . . . . . . . .
E1, E2
. . . . . . . . . . . . . . . . .
VCC
. . . . . . . . . . .
VSS
. . . . . . . . . . . . . . . . . . . . . . .
Address Input
. . . . . . . . . . . . .
Data Input/Data Output
. . .
Write Enable
Output Enable
Chip Enable
Power Supply (+ 5 V)
Ground
PIN NAMES
J PACKAGE
300 MIL SOJ
CASE 810B–03
5
4
3
2
1
10
9
8
7
6
11
12
13
14
20
21
22
23
24
25
26
19
27
28
18
17
16
15
A2
A5
A6
A7
A8
DQ1
A1
A4
VSS
DQ3
DQ2
A3
A0
DQ0
A10
A9
E2
W
VCC
DQ5
DQ6
DQ7
DQ4
E1
G
A11
DQ8
A12
REV 2
5/95
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