參數(shù)資料
型號(hào)： MCM63F733A
廠商： Motorola, Inc.
英文描述： 128K x 32 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
中文描述： 128K的× 32位流通過BurstRAM同步快速靜態(tài)存儲(chǔ)器
文件頁(yè)數(shù)： 9/16頁(yè)
文件大?。?/td> 234K
代理商： MCM63F733A
MCM63F733A
9
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . .
1.25 V
0 to 2.5 V
. . . . . . . . . . . . . .
1.0 V/ns (20 to 80%)
Output Timing Reference Level
Output Load
. . . . . . . . . . . . . .
1.25 V
. . . . . . . . . . . . . . . . . . . . . . . . .
See Figure 2 Unless Otherwise Noted
READ/WRITE CYCLE TIMING
(See Notes 1 through 4)
Parameter
Symbol
b l
MCM63F733A–10
75 MHz
MCM63F733A–11
66 MHz
U i
Unit
Notes
Min
Max
Min
Max
Cycle Time
tKHKH
tKHKL
tKLKH
tKHQV
tGLQV
tKHQX1
tKHQX2
tGLQX
tGHQZ
tKHQZ
tADKH
tADSKH
tDVKH
tWVKH
tEVKH
13
—
15
—
ns
Clock High Pulse Width
5.2
—
6
—
ns
Clock Low Pulse Width
5.2
—
6
—
ns
Clock Access Time
—
10
—
11
ns
Output Enable to Output Valid
—
3.8
—
3.8
ns
Clock High to Output Active
0
—
0
—
ns
5, 6
Clock High to Output Change
1.5
—
1.5
—
ns
6
Output Enable to Output Active
0
—
0
—
ns
5, 6
Output Disable to Q High–Z
—
3.8
—
3.8
ns
5, 6
Clock High to Q High–Z
1.5
3.8
1.5
3.8
ns
5, 6
Setup Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
2
—
2
—
ns
Hold Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHEX
0.5
—
0.5
—
ns
Sleep Mode Standby
tZZS
—
2 x
tKHKH
—
2 x
tKHKH
ns
Sleep Mode Recovery
tZZREC
2 x
tKHKH
—
2 x
tKHKH
—
ns
Sleep Mode High to Q High–Z
tZZQZ
—
15
—
15
ns
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
4. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
5. This parameter is sampled and not 100% tested.
6. Measured at
±
200 mV from steady state.
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