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參數(shù)資料
| 型號： | MCM63P631ATQ75R |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | MS/STANDARD CYLINDRICAL MIL-C-5015 SERIES 3102E ENVIRONMENTAL RESISTING BOX MOUNT RECEPTACLES, STRAIGHT BODY STYLE, SOLDER TERMINATION, 18 SHELL SIZE, 18-11 INSERT ARRANGEMENT, RECEPTACLE GENDER, 5 CONTACTS |
| 中文描述： | 64K X 32 CACHE SRAM, 7 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 228K |
| 代理商： | MCM63P631ATQ75R |
MCM63P631A
7
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS
(See Note 1)
Rating
Symbol
Value
Unit
Notes
Power Supply Voltage
VDD
Vin, Vout
– 0.5 to + 4.6
V
Voltage Relative to VSS for Any
Pin Except VDD
– 0.5 to VDD + 0.5
V
Output Current (per I/O)
Iout
PD
TA
TJ
Tbias
Tstg
±
20
mA
Package Power Dissipation
1.6
W
2
Ambient Temperature
0 to 70
°
C
Die Temperature
110
°
C
2
Temperature Under Bias
– 10 to 85
°
C
Storage Temperature
– 55 to 125
°
C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Rating
Symbol
Max
Unit
Notes
Junction to Ambient (@ 200 lfm)
Single Layer Board
Four Layer Board
R
θ
JA
40
25
°
C/W
1, 2
Junction to Board (Bottom)
R
θ
JB
R
θ
JC
17
°
C/W
3
Junction to Case (Top)
9
°
C/W
4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method
1012.1).
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
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