參數(shù)資料
型號(hào): MCM63P631TQ117R
廠商: MOTOROLA INC
元件分類: DRAM
英文描述: 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
中文描述: 64K X 32 CACHE SRAM, 4.5 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 6/27頁
文件大?。?/td> 328K
代理商: MCM63P631TQ117R
MCM63P636
6
MOTOROLA FAST SRAM
TRUTH TABLE
(See Notes 1 and 2)
K
E
ADS
W
Next Cycle (n)
Input Command Code
DQ (n + 1)
DQ (n+2)
L – H
False
0
X
Deselect
D
High–Z
L – H
True
0
0
Load Address, Begin Write
BW
Data In
L – H
True
0
1
Load Address, Begin Read
BR
Data Out
L – H
X
1
0
Continue Write
CW
Data In
L – H
X
1
1
Continue Read
Mask Write
CR
MW
High–Z
Data Out
NOTES:
1. X = don’t care, 1 = logic high, 0 = logic low.
2. E = true if SE1 and SE3 = 0, and SE2 = 1.
BURST ADDRESS TABLE
1st Address (External)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
2nd Address (Internal)
X . . . X01
X . . . X00
X . . . X11
X . . . X10
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X10
X . . . X01
X . . . X00
DESELECT
NEW
READ*
Figure 1. Functional State Diagram
BURST
READ 1*
BURST
READ 2*
BURST
READ 3*
NEW
WRITE*
BURST
WRITE 1*
BURST
WRITE 2*
BURST
WRITE 3*
MASKED
WRITE 1*
MASKED
WRITE 2*
MASKED
WRITE 3*
D, CW, CR – MW
BR
BW
CR
CR
CR
BR
BW
BW
D, CW, MW
CW
CW
CW
BR
MW
MW
MW
MW
MW
BR
BW
D, CW, MW
D, CW, MW
* Command code inputs not shown from this state are not valid.
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