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參數(shù)資料
| 型號： | MCM67Q909ZP12R |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | Circular Connector; Body Material:Aluminum; Series:PT07; Number of Contacts:4; Connector Shell Size:8; Connecting Termination:Solder; Circular Shell Style:Jam Nut Receptacle; Circular Contact Gender:Pin; Insert Arrangement:8-4 |
| 中文描述： | 512K X 9 STANDARD SRAM, 5 ns, PBGA86 |
| 封裝： | PLASTIC, BGA-86 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 214K |
| 代理商： | MCM67Q909ZP12R |
MCM67C518
1
Motorola, Inc. 1994
32K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Registered Outputs
The MCM67C518 is a 589,824 bit synchronous static random access memory
designed to provide a burstable, high–performance, secondary cache for the
i486
and Pentium
microprocessors. It is organized as 32,768 words of 18 bits,
fabricated with Motorola’s high–performance silicon–gate BiCMOS technology.
The device integrates input registers, a 2–bit counter, high speed SRAM, and
high drive registered output drivers onto a single monolithic circuit for reduced
parts count implementation of cache data RAM applications. Synchronous de-
sign allows precise cycle control with the use of an external clock (K). BiCMOS
circuitry reduces the overall power consumption of the integrated functions for
greater reliability.
Addresses (A0 – A14), data inputs (D0 – D17), and all control signals except
output enable (G) are clock (K) controlled through positive–edge–triggered non-
inverting registers.
This device contains output registers for pipeline operations. At the rising edge
of K, the RAM provides the output data from the previous cycle.
Output enable (G) is asynchronous for maximum system design flexibility.
Burst can be initiated with either address status processor (ADSP) or address
status cache controller (ADSC) input pins. Subsequent burst addresses can be
generated internally by the MCM67C518 (burst sequence imitates that of the
i486) and controlled by the burst address advance (ADV) input pin. The following
pages provide more detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased flexibility for incoming signals.
Dual write enables (LW and UW) are provided to allow individually writeable
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17
(the upper bits).
This device is ideally suited for systems that require wide data bus widths and
cache memory. See Figure 2 for applications information.
Single 5 V
±
5% Power Supply
Fast Access Time/Fast Cycle Time = 6 ns/100 MHz, 7 ns/80 MHz, 9 ns/66 MHz
Byte Writeable via Dual Write Enables
Internal Input Registers (Address, Data, Control)
Output Registers for Pipelined Applications
Internally Self–Timed Write Cycle
ADSP, ADSC, and ADV Burst Control Pins
Asynchronous Output Enable Controlled Three–State Outputs
Common Data Inputs and Data Outputs
3.3 V I/O Compatible
High Board Density 52–Lead PLCC Package
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
PIN ASSIGNMENTS
10
11
9
8
DQ9
DQ10
VCC
VSS
DQ5
DQ8
DQ7
12
13
15
16
14
17
18
20
21 22 23 24 25 26 2728 29 30 31 3233
19
37
36
38
34
35
42
41
43
39
40
45
44
46
7
6
5 4
3 2
1 52 51 50 49 4847
DQ6
DQ4
DQ3
DQ2
VSS
VCC
DQ1
DQ0
VCC
VSS
DQ11
DQ12
DQ13
DQ14
VSS
VCC
DQ15
DQ16
DQ17
A
A
E
U
K
A
A
A
L
A
G
A
A
N
A
A
A
A
A
A
A
A
V
A
A
V
All power supply and ground pins must be
connected for proper operation of the device.
PIN NAMES
A0 – A14
K
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADV
. . . . . . . . . . . .
LW
. . . . . . . . . . . .
UW
. . . . . . . . . . . .
ADSC
Controller Address Status
. . . . . . . . .
ADSP
Processor Address Status
. . . . . . . . .
E
. . . . . . . . . . . . . . . . . . . . . . . . .
G
. . . . . . . . . . . . . . . . . . . . . .
DQ0 – DQ17
. . . . . . . . . .
VCC
. . . . . . . . . . . . . . . .
VSS
. . . . . . . . . . . . . . . . . . . . . . . . . .
NC
. . . . . . . . . . . . . . . . . . . . .
Address Inputs
. . . . . . . . . . . . . . . .
Clock
Burst Address Advance
Lower Byte Write Enable
Upper Byte Write Enable
Chip Enable
Output Enable
Data Input/Output
+ 5 V Power Supply
Ground
No Connection
Order this document
by MCM67C518/D
SEMICONDUCTOR TECHNICAL DATA
MCM67C518
FN PACKAGE
PLASTIC
CASE 778–02
REV 3
5/95
相關(guān)PDF資料 |
PDF描述 |
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| MCM67C618FN6 | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| MCM67H518 | 32K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| MCM67H518FN10 | 32K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| MCM67H518FN12 | 32K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| MCM67H518FN9 | 32K x 18 Bit BurstRAM Synchronous Fast Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM67T415 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:16K x 15 Bit Cache Tag RAM for Pentium Processors |
| MCM67T415TQ | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:16K x 15 Bit Cache Tag RAM for Pentium Processors |
| MCM6810 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128 8-bit Random-Access Memory |
| MCM6810P | 制造商:Motorola 功能描述:6810 MOT NOTES 制造商:Motorola Inc 功能描述: |
| MCM68766 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:B192*8BIT UV ERASABLE PROM |
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