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參數(shù)資料
| 型號(hào)： | MCM67T415TQ |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16K x 15 Bit Cache Tag RAM for Pentium Processors |
| 中文描述： | 16K的× 15位高速緩存標(biāo)記RAM的奔騰處理器 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 214K |
| 代理商： | MCM67T415TQ |
MCM67C518
2
MOTOROLA FAST SRAM
BLOCK DIAGRAM
(See Note)
DQ0 – DQ8
CLR
Q0
Q1
A0
A1
K
ADSC
ADSP
A0 – A14
E
G
ADDRESS
REGISTER
WRITE
REGISTER
ENABLE
REGISTER
DATA–IN
REGISTERS
OUTPUT
BUFFER
32K x 18
MEMORY
ARRAY
ADV
BURST LOGIC
INTERNAL
ADDRESS
A0
′
A1
′
15
9
18
15
2
A2 – A14
A1 – A0
DQ9 – DQ17
9
9
9
9
9
BINARY
COUNTER
DATA–OUT
REGISTERS
UW
LW
NOTE:
All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is per-
formed using the new external address. Alternatively, an ADSP–initiated two cycle WRITE can be performed by asserting
ADSP and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW with valid
data on the second cycle (see Single Write cycle in WRITE CYCLES timing diagram).
When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent
on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded.
After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address is
advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait state
into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See
BURST
SEQUENCE TABLE
. Write refers to either or both byte write enables (LW, UW).
BURST SEQUENCE TABLE
(See Note)
External Address
A14 – A2
A1
A0
1st Burst Address
A14 – A2
A1
A0
2nd Burst Address
A14 – A2
A1
A0
3rd Burst Address
A14 – A2
A1
A0
NOTE: The burst wraps around to its initial state upon completion.
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