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參數(shù)資料
| 型號(hào)： | MCM69P536CTQ4.5R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 32K X 36 CACHE SRAM, 4.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 210K |
| 代理商： | MCM69P536CTQ4.5R |
MCM69P536C
5
MOTOROLA FAST SRAM
TRUTH TABLE
(See Notes 1 through 4)
Next Cycle
Address
Used
SE1
SE2
SE3
ADSP
ADSC
ADV
G 3
DQx
Write 2, 4
Deselect
Deselect
Deselect
Deselect
Deselect
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
NOTES: 1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times.
G must also remain negated at the completion of the write cycle to ensure proper write data hold times.
None
None
None
None
None
External
External
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
External
Next
Next
Current
Current
1
0
0
X
X
0
0
X
X
1
1
X
X
1
1
X
1
0
X
1
X
1
X
X
0
X
0
1
1
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
1
X
1
X
0
0
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
1
X
1
1
X
1
X
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
1
1
X
0
0
1
1
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
DQ
High–Z
DQ
High–Z
DQ
High–Z
DQ
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
X
X
X
X
X
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
LINEAR BURST ADDRESS TABLE
(LBO = VSS)
1st Address (External)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
2nd Address (Internal)
X . . . X01
X . . . X10
X . . . X11
X . . . X00
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE
(LBO = VDD)
1st Address (External)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
2nd Address (Internal)
X . . . X01
X . . . X00
X . . . X11
X . . . X10
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X10
X . . . X01
X . . . X00
WRITE TRUTH TABLE
Cycle Type
SGW
H
H
H
H
H
H
H
L
SW
H
L
L
L
L
L
L
X
SBa
X
H
L
H
H
H
L
X
SBb
X
H
H
L
H
H
L
X
SBc
X
H
H
H
L
H
L
X
SBd
X
H
H
H
H
L
L
X
Read
Read
Write Byte a
Write Byte b
Write Byte c
Write Byte d
Write All Bytes
Write All Bytes
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM69P536CTQ4R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM69P536CTQ5 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM69P536CTQ5R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM69P536CTQ6 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM69P536CTQ6R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
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